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smsc ds ? LAN91C96I page 1 rev. 03-28-07 datasheet LAN91C96I non-pci single-chip full duplex ethernet controller datasheet product features ? non-pci single-chip ethernet controller ? fully supports full duplex switched ethernet ? supports enhanced transmit queue management ? 6k bytes of on-chip ram ? supports ieee 802.3 (ansi 8802-3) ethernet standards ? automatic detection of tx/rx polarity reversal ? enhanced power management features ? supports ?magic packet? power management technology ? simultasking early transmit and early receive functions ? enhanced early transmit function ? receive counter for enhanced early receive ? hardware memory management unit ? optional configurati on via serial eeprom interface (jumperless) ? supports single 5v or 3.3v vcc design ? industrial temperature range of ?40 c to 85 c ? supports mixed voltage external phy designs 1 ? low power cmos design ? 100 pin qfp and tqfp (1.0mm body thickness) packages; lead-free packages also available ? pin compatible with the lan91c92 and lan91c94 bus interface ? direct interface to local bu s, with no wait states ? flexible bus interface ? 16 bit data and control paths ? fast access time 1 refer to description of pi n functions on page 14 for 5v tolerant pins ? pipelined data path ? handles block word transfers for any alignment ? high performance chained ("back-to-back") transmit and receive ? pin compatible with the lan91c92 and the lan91c94 in local bus mode ? dynamic memory allocation between transmit and receive ? flat memory structure for low cpu overhead ? buffered architecture, insensitive to bus latencies (no overruns/underruns) ? supports boot prom for diskless local bus applications network interface ? integrated 10base-t transceiver functions: - driver and receiver - link integrity test - receive polarity detection and correction ? integrated aui interface ? 10 mb/s manchester encoding/decoding and clock recovery ? automatic retransmission, bad packet rejection, and transmit padding ? external and internal loopback modes ? four direct driven leds for status/ diagnostics software drivers ? lan9000 drivers for major network operating systems utilizing local bus interface ? software drivers compatible with the lan91c92, lan91c94, lan91c100fd (100 mb/s), and lan91c110 (100 mb/s) controllers in local bus mode ? software drivers utilize full capability of 32 bit microprocessor
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 2 smsc ds ? LAN91C96I datasheet ordering information order numbers: LAN91C96Iqfp for 100 pin qfp package LAN91C96Itqfp for 100 pin tqfp package LAN91C96I-mu for 100 pin tqfp package (green, lead-free) LAN91C96I-ms for 100 pin qfp package (green, lead-free) 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2007 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for c onstruction purposes is not necessarily given. although the information has been checked and is bel ieved to be accurate, no responsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to obtain the la test specifications before placi ng your product order. the provisi on of this information does not convey to the purchaser of the described semiconductor devic es any licenses under any patent ri ghts or other intellectual p roperty rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (t he "terms of sale agreement"). the product may contain design def ects or errors known as anomalies which may caus e the product's functions to deviate from publis hed specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where produc t failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at t he risk of the customer. copies of this do cument or other smsc literature, as wel l as the terms of sale agreement, may be obtained by visiting smsc?s website at http://www .smsc.com. smsc is a registered trademark of standard micros ystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and a ll warranties, including without limitation any and all implied warranties of merchantability, fitn ess for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usag e of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of smsc or others; strict liability; breach of warranty; or othe rwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether or no t smsc has been advised of the possibility of such damages.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 3 rev. 03-28-07 datasheet table of contents chapter 1 general description ............................................................................................................ .5 chapter 2 overview ....................................................................................................................... ........ 6 chapter 3 pin configurations ............................................................................................................. .. 9 3.1 local bus vs. pi n require ments ................................................................................................. ...... 12 chapter 4 description of pin functions ............................................................................................. 14 4.1 buffer sy mbols ................................................................................................................. ................. 17 chapter 5 functional description....................................................................................................... 19 5.1 buffer memory .................................................................................................................. ................. 20 5.2 interrupt st ructure ............................................................................................................ ................. 26 5.3 reset logic.................................................................................................................... .................... 27 5.4 power down logic st ates ........................................................................................................ ......... 27 chapter 6 packet format in buffer memory for ethernet............................................................... 29 chapter 7 registers map in i/o space............................................................................................... 32 7.1 i/o space access............................................................................................................... ............... 33 7.2 i/o space regist ers description ................................................................................................ ....... 34 7.2.1 bank select regi ster ........................................................................................................... ...................34 chapter 8 theory of operation .......................................................................................................... 58 8.1 typical flow of events for tr ansmit (auto re lease =0).................................................................. 60 8.2 typical flow of events for tr ansmit (auto re lease = 1)................................................................... 61 8.3 typical flow of ev ents for receive ............................................................................................. .... 62 8.4 memory part itioning ............................................................................................................ .............. 68 8.5 interrupt ge neration ........................................................................................................... ............... 68 8.6 power down ..................................................................................................................... ................. 70 chapter 9 functional description of the blocks................................................................................ 72 9.1 memory man agement unit ......................................................................................................... ....... 72 9.2 arbiter ........................................................................................................................ ........................ 72 9.3 bus interface .................................................................................................................. ................... 73 9.4 wait stat e policy .............................................................................................................. ................. 73 9.5 arbitration co nsiderat ions ..................................................................................................... ............ 74 9.6 dma block...................................................................................................................... ................... 74 9.7 packet number fifos............................................................................................................ ........... 75 9.8 csma block ..................................................................................................................... ................. 76 9.9 network in terface .............................................................................................................. ................ 78 9.10 10base-t ....................................................................................................................... ............... 78 9.11 aui ............................................................................................................................ ..................... 78 9.12 physical interface............................................................................................................. .............. 79 9.13 transmit functions............................................................................................................. ............ 79 9.14 transmit drivers............................................................................................................... .............. 79 9.15 receive fu nctions.............................................................................................................. ............ 79 chapter 10 board setup information ............................................................................................... 81 10.1 diagnostic leds................................................................................................................ ............. 82 10.2 bus clock cons iderations ....................................................................................................... ....... 82 chapter 11 operation description .................................................................................................... 84 11.1 maximum guarant eed ratings*.................................................................................................... .84 11.2 dc electrical characteristics .................................................................................................. ....... 85 chapter 12 timing diagrams ............................................................................................................ 91
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 4 smsc ds ? LAN91C96I datasheet chapter 13 package outlines........................................................................................................... 108 list of figures figure 3.1 ? pin c onfiguration of LAN91C96I qfp................................................................................ ........................9 figure 3.2 pin configuration of lan91c 96i tqfp........................................................................................... .........10 figure 3.3 ? system diagram for local bu s with b oot pr om ....................................................................... ................11 figure 4.1 - LAN91C96I in ternal blo ck diagram .................................................................................. ........................18 figure 5.1 ? mapping and paging vs. receive and transmit area .................................................................. ............21 figure 5.2 ? transmit queues and mapping....................................................................................... .........................22 figure 5.3 ? receive queues and mapping........................................................................................ .........................23 figure 5.4 ? LAN91C96I internal block diagram wi th data path ................................................................... ..............24 figure 5.5 ? logical address gener ation and relev ant regi sters................................................................. ..............25 figure 6.1 ? data packet format ................................................................................................ .................................29 figure 7.1 - lan91c 96i registers ............................................................................................... ................................32 figure 7.2 ? interr upt structure ............................................................................................... .....................................54 figure 8.1 ? interrupt service routine ......................................................................................... ................................63 figure 8.2 ? rx intr........................................................................................................... ........................................64 figure 8.3 ? tx intr ........................................................................................................... ........................................65 figure 8.4 ? tx empty intr...................................................................................................... .................................66 figure 8.5 ? driver send and allocate routines ................................................................................. .........................67 figure 8.6 ? interrupt generati on for transmit; receive, mmu ................................................................... ................71 figure 9.1 - mmu packet number fl ow and relevant registers ..................................................................... ............76 figure 10.1 - 64 x 16 serial eepr om map........................................................................................ .........................83 figure 12.1 ? local bus consecutive read cycles................................................................................ .......................91 figure 12.2 ? local bus co nsecutive write cycles ............................................................................... ........................92 figure 12.3 ? local bus consecut ive read and write cycles...................................................................... .................93 figure 12.4 ? data regist er special read a ccess ................................................................................ ......................94 figure 12.5 ? data regist er special wr ite a ccess............................................................................... ........................95 figure 12.6 - 8-bit m ode register cycles ....................................................................................... .............................96 figure 12.7 ? external rom read access ......................................................................................... .........................97 figure 12.8 ? local bus regist er access when using bale ........................................................................ .................98 figure 12.9 ? external ro m read access using bale .............................................................................. ..................99 figure 12.10 - eeprom read..................................................................................................... ..............................100 figure 12.11 - eeprom write .................................................................................................... ...............................101 figure 12.12 ? external endec interface ? start of transmi t .................................................................... ...............102 figure 12.13 ? external ende c interface ? receive data ......................................................................... ...............102 figure 12.14 ? differential output signal timing (10base-t and au i) ............................................................ .........103 figure 12.15 ? receive timing ? st art of frame (a ui and 10 base-t) .............................................................. .......104 figure 12.16 ? receive timing ? end of frame (a ui and 10 base-t)................................................................ .......105 figure 12.17 ? transmit timing ? end of frame (a ui and 10 base-t)............................................................... .......105 figure 12.18 ? collis ion timing (aui) .......................................................................................... ..............................106 figure 12.19 ? memo ry read timing.............................................................................................. ...........................106 figure 12.20 ? i nput clock timing .............................................................................................. ...............................107 figure 12.21 ? memo ry write timing ............................................................................................. ............................107 figure 13.1 - 100 pin qfp package outline ...................................................................................... ........................108 figure 13.2 - 100 pin tq fp package outline ..................................................................................... .......................109 list of tables table 5.1 - LAN91C96I address space ............................................................................................ ...........................26 table 5.2 - bus transacti ons in loca l bus mode ................................................................................. ........................26 table 5.3 ? inte rrupt me rging .................................................................................................. .....................................26 table 5.4 ? reset logic ........................................................................................................ .......................................27 table 5.5 - local bus mode defined st ates (refer to table 5.6 for ne xt states to wa ke-up ev ents)......................28 table 5.6 - loc al bus mode ..................................................................................................... ....................................28 table 7.1 - tr ansmit loop ...................................................................................................... ......................................36 table 13.1 - 100 pin qf p package pa rameters .................................................................................... ....................108 table 13.2 - 100 pin tq fp package pa rameters ................................................................................... ...................109
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 5 rev. 03-28-07 datasheet chapter 1 general description the LAN91C96I is a vlsi ethernet controller that co mbines local bus interfaces in one chip. LAN91C96I integrates all mac and physical la yer functions, as well as the packet ram, needed to implement a high performance 10base-t (twisted pair) node. for 10bas e5 (thick coax), 10base2 (thin coax), and 10base-f (fiber) implementations, the LAN91C96I interfaces to external transceivers via the provided aui port. only one additional ic is required for most applications. the LAN91C96I comes with full duplex switched ethernet (fdswe) support allowing the cont roller to provide much higher throughput. 6k bytes of ram is provided to support enhanced throughput and compensate for any increased system service latencies. the controller implem ents multiple advanced powerdown modes including magic packet to conserve power and operate more efficiently. the lan9 1c96i can directly interface with the local bus and deliver no-wait-state operation. for local bus interf aces, the LAN91C96I occupies 16 i/0 locations and no memory space. the same i/o space is used for local bus operations. its shared memory is sequentially accessed with 40ns access times to any of its registers, including it s packet memory. dma services are not used by the LAN91C96I, virtually decoupling network traffic from local or system bus utilization. for packet memory management, the LAN91C96I integrates a unique ha rdware memory management unit (mmu) with enhanced performance and decreased software overhead when compared to ring buffer and linked list architectures. the LAN91C96I is portable to diffe rent cpu and bus platforms due to its flexible bus interface, flat memory structure (n o pointers), and its loosely coupled buffe red architecture (not sensitive to latency). the LAN91C96I is available in 100-pin qfp and tqfp (1.0 mm body thickness) packages; green, lead- free packages are also available. the low profile tqfp is ideal for mobile applications such as pc card lan adapters. the LAN91C96I operates with a single po wer supply voltage of 5v or 3.3v. the industrial temperature range for LAN91C96I is ?40 q c to 85 q c.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 6 smsc ds ? LAN91C96I datasheet chapter 2 overview a unique architecture allows the LAN91C96I to comb ine high performance, flexibility, high integration and simple software interface. the LAN91C96I incorporates the lan91c92 functi onality for local bus environments. the LAN91C96I consists of the same logical i/o register structure in local bus modes. t he mmu (memory management unit) architecture used by the LAN91C96I combines the simplicity and low overhead of fixed areas with the flexibility of linked lists providing improved performance over other methods. packet reception and transmission are determined by memo ry availability. all other resources are always available if memory is available. to complement th is flexible architecture, bus interface functions are incorporated in the LAN91C96I, as well as a 6144 by te packet ram - and serial eeprom-based setup. the user can select or modify configuration choice s. the LAN91C96I integr ates most of the 802.3 functionality, incorporating the ma c layer protocol, the physical layer encoding and decoding functions with the ability to handle the aui in terface. for twisted pair networks, LAN91C96I integrates the twisted pair transceiver as well as the link integrity test functions. the LAN91C96I is a true 10base-t single chip device able to interface to a system or a local bus. support for direct-driven leds for installation and r un-time diagnostics is provided. 802.3 statistics are gathered to facilitate network management. the LAN91C96I is a single chip ethernet controller designed to be 100% pin and software compatible with the lan91c92 and lan91c94 in local bus mode. the LAN91C96I has been designed to support full dupl ex switched ethernet and provides fully independent transmit and receive operations. the LAN91C96I internal packet memory is extended to 6k bytes, and the mmu will continue to manage memory in 256 byte pages. the increase in memory size accommodates the potential for simultaneous transmit and receive traffic in some full duplex appl ications as well as support for enhanced performance on systems that introduce increased latency. the LAN91C96I has the ability to retrieve configuration information from a serial eeprom on reset or power- up. in local bus mode, the serial eeprom acts as storage of configuration and ieee ethernet address information compatible with the existing lan91c90, lan91c92, and lan91c94 local bus ethernet controllers. external flash rom is required for cis storage.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 7 rev. 03-28-07 datasheet the LAN91C96I offers: high integration: single chip controller including: ? packet ram ? local bus interface ? eeprom interface ? encoder/decoder with aui interface ? 10base-t transceiver high performance: chained ("back-to-back") packet handling with no cpu intervention: ? queues transmit packets ? queues receive packets ? stores results in memory along with packet ? queues interrupts ? optional single interrupt upon completion of transmit chain fast block move operation for load/unload: ? cpu sees packet bytes as if stored continuously. ? handles 16 bit transfers regardless of address alignment. ? access to packet through fixed window. fast bus interface: compatible with local bus type and faster buses. flexibility: flexible packet and header processing: ? can be set to simultasking - early receive and transmit modes. with enhanced early receive functions. ? can access any byte in the packet. ? can immediately remove undesired packets from queue. ? can move packets from receive to transmit queue.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 8 smsc ds ? LAN91C96I datasheet ? can alter receive processing order without copying data. ? can discard or enqueue again a failed transmission. resource allocation: ? memory dynamically allocated for transmit and receive. ? can automatically release memory on successful transmission. configuration: local bus: ? uses non-volatile jumperless setup via serial eeprom. ? nromon LAN91C96I, is left open with a pullup for local bus mode. this pin is sampled at the end of reset.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 9 rev. 03-28-07 datasheet chapter 3 pin configurations avdd coln colp recn recp tperxn tperxp avss avss rbias avdd nxendec nen16 vss nrom xtal1 xtal2 ios0 ios1 vdd 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 niocs16/niois16 vss a2 a0 a1 bale/nwe nsbhe/nce2 intr3 intr20 vdd intr1/ninpack d15 d14 d13 d12 vdd d11 d10 d9 d8 vss eesk eedi eedo/sdout eneep vss eecs ios2 vss intr0/nireq/intr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 23 24 25 26 2728 29 30 vdd a19/nce1 a18 a17 a16 a15 a14 a13 a12 a11/nfcs vdd a10/nfwe a9 a8 a7 a6 a5 a4 a3 vss 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 LAN91C96I 100 pin qfp 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ntxled/ntxen pwrdwn/txclk niord/xds niowr/r/nw nmemr/noe aen/nreg/nas iochrdy/nwait vss d0 d1 d2 d3 vdd d4 d5 d6 d7 vss reset bseled/rxd nlnkled/txd nrxled/rxclk avdd tpetxdp tpetxdn tpetxp txn/ncrs txp/ncoll avss tpetxn figure 3.1 ? pin configuration of LAN91C96I qfp
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 10 smsc ds ? LAN91C96I datasheet eneep eedo/sdout eedi eecs eesk vss d8 d9 d10 d11 vdd d12 d13 d14 d15 vss intr0/nireq/intr intr1/ninpack vdd intr2 intr3 vss niocs16/niois16 nsbhe/nce2 bale/nwe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 a0 a1 a2 vss a3 a4 a5 a6 a7 a8 a9 a10/nfwe vdd a11/nfcs a12 a13 a14 a15 a16 a17 a18 a19/nce1 vdd niord/xds niowr/r/nw 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 tpetxp tpetxdn tpetxn tpetxdp avdd ntxled/ntxen nrxled/rxclk nlnkled/txd nbseled/rxd pwrdwn/txclk reset vss d7 d6 d5 d4 vdd d3 d2 d1 d0 vss iochrdy/nwait aen/nreg/nas nmemr/oe 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vss ios2 vdd ios1 ios0 xtal2 xtal1 nrom vss nen16 nxendec avdd rbias avss avss tperxp tperxn recp recn colp coln avdd avss txp/ncoll txn/ncrs 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 LAN91C96I 100 pin tqfp figure 3.2 pin configuration of LAN91C96I tqfp
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 11 rev. 03-28-07 datasheet figure 3.3 ? system diagram for local bus with boot prom t p e t x p t p e t x n t p e t x d p t p e t x d n t p e r x p t p e r x n t x p t x n r e c p r e c n c o l p c o l n x t a l 1 x t a l 2 e e d i e e c s e e d o e e s k i o s 0 i o s 1 i o s 2 e n e e p a e n r e s e t n s b h e n i o r d , n i o w r , n m e m r d 0 - 1 5 a 0 - 1 9 n r o m n i o c s 1 6 i o c h r d y i n t r 0 - 3 cable side 4 s e r i a l e e p r o m 4 2 0 m h z 3 s y s t e m b u s a d d re s s p r o m d a t a n i r q la n 9 1 c 9 6 i r b i a s b u f f e r diagnostic leds 10baset aui n e n 1 6 b a l e n / c 4
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 12 smsc ds ? LAN91C96I datasheet 3.1 local bus vs. pin requirements function local bus max number of pins system address bus a0 a1-9 a10 a11 a12-14 a15 a16-18 a19 aen 21 system data bus d0-15 16 system control bus reset bale niord niowr nmemr iochrdy niocs16 nsbhe intr0 intr1 intr2 intr3 12 serial eeprom eedi eedo eecs eesk eneep ios0 ios1 ios2 8 crystal osc. xtal1, xtal2 2 power vdd, avdd 9 ground gnd, agnd 11 10base-t interface tperxp tperxn tpetxp tpetxn tpetxdp tpetxdn 6 aui interface recp recn colp coln txp/ncoll txn/ncrs 6
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 13 rev. 03-28-07 datasheet function local bus max number of pins leds nlnkled/ txd nrxled/ rxclk nbseled/ rxd ntxled/ ntxen 4 misc. rbias pwrdwn/txcl k nxendec nen16 nrom 5
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 14 smsc ds ? LAN91C96I datasheet chapter 4 description of pin functions pin no. tqfp qfp pin name type description 93 95 nrom i/o4 with pullup this pin is sampled at the end of reset. for local bus operation this pin is left open and it is used as a rom chip select output that goes active when nmemr is low and the address bus contains a valid rom address. in local bus mode the LAN91C96I is pin com patible with the lan91c92 and lan91c94 26-28 30-36 28,29, 30, 32-38 a0-9 i ** input address lines 0 through 9. 37 39 a10/nfwe i local bus - input address line 10. 39 41 a11/nfcs i local bus - input address line 11. 40-46 42-48 a12-18 i ** input address lines 12 through 18. 47 49 a19/nce1 i with pullup local bus - input address line 19. 52 54 aen/ nreg/ nas i with pullup ** local bus - address enable input. used as an address qualifier. address decoding is only enabled when aen is low. 24 26 nsbhe/ nce2 i with pullup ** local bus - byte high enable input. asserted (low) by the system to indicate a data transfer on the upper data byte. 53 55 iochrdy/ nwait od24 with pullup local bus - output. optionally used by the LAN91C96I to extend host cycles. 55-58 60-63 7- 10 12-15 57-60, 62-65, 9-12, 14-17 d0-15 i/o24 bi-directional. 16 bit data bus used to access the LAN91C96I internal registers. the data bus has weak internal pullups. supports direct connection to the system bus without external buffering. 65 67 reset is with pullup ** input. active high reset. this input is not considered active unless it is active for at least 100ns to filter narrow glitches. 25 27 bale/nwe is with pullup ** local bus - input. address strobe. for systems that require address latching, the falling edge of bale latches address lines and nsbhe. 17 19 intr0/ nireq/ intr o24 local bus - active high interrupt signal. the interrupt line selection is determined by the value of int sel1-0 bits in the configuration register. this in terrupt is tri-stated when not selected. 18 20 intr1/ ninpack o24 local bus - output. active high interrupt signal. the interrupt line selection is determined by the value of int sel1-0 bits in the configuration register. th is interrupt is tri-stated when not selected. 20 22 intr2 o24 local bus - outputs. active high interrupt signals. the interrupt line selection is determined by the value of int sel1-0 bits in the configurat ion register. these interrupts are tri-stated when not selected.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 15 rev. 03-28-07 datasheet pin no. tqfp qfp pin name type description 21 23 intr3 o24 local bus - outputs. active high interrupt signals. the interrupt line selection is determined by the value of int sel1-0 bits in the configurat ion register. these interrupts are tri-stated when not selected. 23 25 niocs16/ niois16 od24 local bus - active low output asserted in 16 bit mode when aen is low and a4-a15 decode to the LAN91C96I address programmed into the high byte of the base address register. 49 51 niord/ xds is with pullup ** local bus, - input. active low read strobe used to access the LAN91C96I io space. 50 52 niowr/ r/nw is with pullup ** local bus - input. active low write strobe used to access the LAN91C96I io space. 51 53 nmemr/ noe is with pullup ** local bus - active low signal used by the host processor to read from the external rom. 5 7 eesk o4 output. 4usec clock used to shi ft data in and out of a serial eeprom. 4 6 eecs o4 output. seri al eeprom chip select. 2 4 eedo/ sdout o4 output. connected to the di input of the serial eeprom. 3 5 eedi i with pull- down ** input. connected to the do ou tput of the serial eeprom. 96,97 98,99 ios0-1 i with pullup input. external switches can be connected to these lines to select between predefined eeprom configurations. the values of these pins are readable. 99 1 ios2 i with pullup ** input. external switches can be connected to these lines to select between predefined eeprom configurations. the values of these pins are readable. 70 72 ntxled/ ntxen od16 internal endec - transmit led output. o162 external endec - active low transmit enable output. 67 69 nbseled/ rxd od16 internal endec - board select led activated by accesses to i/o space (niord or niowr active with aen low and valid address decode for local bus). the pulse is stretched beyond the access duration to make the led visible. i with pullup external endec - nrz receive data input. 69 71 nrxled/ rxclk od16 internal endec - receive led output. i with pullup external endec - receive clock input. 68 70 nlnkled/ txd od16 internal endec - link led output. o162 external endec - transmit data output.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 16 smsc ds ? LAN91C96I datasheet pin no. tqfp qfp pin name type description 1 3 eneep i with pullup ** input. this active high input enables the eeprom to be read or written by the LAN91C96I. internally pulled up. must be connected to ground if no serial eeprom is used. 91 93 nen16 i with pullup ** input. when low the LAN91C96I is configured for 16 bit bus operation. if left open the LAN91C96I works in 8 bit bus mode. 16 bit configuration can also be programmed via serial eeprom or software initiali zation of the configuration register. 94 96 xtal1 iclk ** an external parallel resonance 20mhz crystal should be connected across these pins. if an external clock source is used, it should be connected to this pin (xtal1) and xtal2 should be left open. 95 97 xtal2 iclk an external parallel resonance 20mhz crystal should be connected across these pins. if an external clock source is used, it should be connected to xtal1 and this pin (xtal2) should be left open. 83 82 85 84 recp/ recn diff. input ** aui receive differential inputs. 77 76 79 78 txp/ncoll txn/ncrs diff. output internal endec - (nxendec pin open). in this mode txp and txn are the aui transmit differential outputs. they must be externally pulled up using 150 ohm resistors. i ** external endec - (nxendec pin tied low). in this mode the pins are inputs used for collision and carrier sense functions. 81 80 83 82 colp coln diff. input ** aui collision differential inputs. a collision is indicated by a 10mhz signal at this input pair. 85 84 87 86 tperxp tperxn diff. input ** 10base-t receive differential inputs. 75 73 77 75 tpetxp tpetxn diff. output internal endec - 10base-t transmit differential outputs. 72 74 74 76 tpetxdp tpetxdn diff. output 10base-t delayed transmit differential outputs. used in combination with tpetxp and tpetxn to generate the 10base-t transmit pre-distortion. 66 68 pwrdwn/ txclk i with pullup ** internal endec - powerdown input. it keeps the LAN91C96I in powerdown mode when high (open). must be low for normal operation. external endec - transmit clock input from external endec. 88 90 rbias analog input a resistor should be connected between this pin and analog ground to determine the threshol d level of the tp receive, aui receive, aui collision and aui transmit level. 90 92 nxendec i with pullup ** when tied low the LAN91C96I is configured for external endec. when tied high or left open the LAN91C96I will use its internal encoder/decoder. 11,19, 48,59, 98,38 13,21,40, 50, 61,100 vdd +5.0v power supply pins or 3.3v power supply pins
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 17 rev. 03-28-07 datasheet pin no. tqfp qfp pin name type description 71,79, 89 73,81, 91 avdd +5.0v analog power supply pins or 3.3v power supply pins 100,6, 22,29 54,64,92 ,16 2,8,18, 24,31, 56,66, 94 gnd ground pins. 78,86 87 80,88,89 agnd analog ground pins. 4.1 buffer symbols o4 output buffer with 2ma source and 4ma sink at 5v. output buffer with 1ma source and 2ma sink at 3.3v. i/o4 output buffer with 2ma source and 4ma sink at 5v. output buffer with 1ma source and 2ma sink at 3.3v. o162 output buffer with 2ma source and 16ma sink at 5v. output buffer with 1ma source and 8ma sink at 3.3v. o24 output buffer with 12ma source and 24ma sink at 5v. output buffer with 6ma source and 12ma sink at 3.3v. od16 open drain buffer with 16ma sink at 5v. open drain buffer with 8ma sink at 3.3v. od24 open drain buffer with 24ma sink at 5v. open drain buffer with 12ma sink at 3.3v. i/o24 bi-directional buffer with 12ma source and 24ma sink at 5v. bi-directional buffer with 6ma source and 16ma sink at 3.3v. i input buffer with ttl levels. is input buffer with schmitt trigger hysteresis. iclk clock input buffer. ** signal is 5.0v input tolerant when v cc =3.3v. dc levels and conditions defined in the dc electrical characteristics section.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 18 smsc ds ? LAN91C96I datasheet figure 4.1 - LAN91C96I internal block diagram databu a ddres bus control bus interfac a rbite csma/c ende a ui mmu twisted transceive 10base- ram
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 19 rev. 03-28-07 datasheet chapter 5 functional description the LAN91C96I includes an arbitrated-shared memory of 6144 bytes. any portion of this memory can be used for receive or transmit packets. the mmu unit allocates ram memory to be used for transmit and receive packets, using 256 byte pages. the arbitration is transparent to the cp u in every sense. there is no speed penalty for local bus type of machines due to arbitration. ther e are no restrictions on what loca tions can be accessed at any time. ram accesses as well as mmu requests are arbitrated. the ram is accessed by mapping it into i/o space for sequential access. except for the ram accesses and the mmu request/release commands , i/o accesses are not arbitrated. the i/o space is 16 bits wide. provisions for 8 bit systems are handled by the bus interface. in the system memory space, up to 64 kbytes are decoded by the LAN91C96I as expansion rom. the rom expansion area is 8 bits wide. device configuration is done using a serial eeprom, with suppor t for modifications to the eeprom at installation time. the csma/cd core implements the 802.3 mac layer prot ocol. it has two independent interfaces, the data path and the control path. in local bus mode, serial eeprom is used for config uration and ieee node address making it software compatible to the lan9xxx family of ethernet lan controllers. the eeprom is optional for local bus requiring a minimum size of 64 x 16 bit word addresses. both interfaces are 16 bits wide. the control path prov ides a set of registers used to configure and control the block. these registers are accessible by the cpu through the LAN91C96I i/o space. the data path is of sequential access nature and typically works in one direction at any given time. an internal dma type of interface connects the data path to t he device ram through the arbiter and mmu. the csma/cd data path interface is not accessible to the host cpu. the internal dma interface can arbitrate for ra m access and request memory from the mmu when necessary. an encoder/decoder block interfaces the csma/cd block on the serial side. the encoder will do the manchester encoding of the transmit data at 10 mb/s, while the decoder w ill recover the receive clock, and decode received data. carrier and collision detection signals are also handle d by this block and relayed to the csma/cd block. the encoder/decoder block can interface the network through the aui interface pairs, or it can be programmed to use the internal 10base-t transceiv er and connect to a twisted pair network. the twisted pair interface takes care of the medium dependent signaling for 10base-t type of networks. it is responsible for line interface (with external pulse transformers and pre-distortion resistors), collision detection as well as the link integrity test function. the LAN91C96I provides a 16-bit data path into ra m. the ram is private and can only be accessed by the system via the arbiter. ram memory is managed by the mmu. byte and word accesses to the ram are supported.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 20 smsc ds ? LAN91C96I datasheet if the system to sram bandwidth is insufficient the LAN91C96I will automatically use its iochrdy line for flow control. however, for local bus, iochrdy will never be negated. the LAN91C96I consists of an integrated ethernet controller mapped entirely in i/o space. the ethernet controller function includes a built-in 6kbyte ram for packet storage. this ram buffer is accessed by the cpu through sequential access regions of 256 bytes each. the ram access is internally arbitrated by the LAN91C96I, and dynamically allocate d between transmit and receive packets. each packet may consist of one or more 256 byte page. the ethernet controller functionality is identical to the lan91c94 and lan91c95 except where indicated otherwise. the LAN91C96I memory management unit parameters are: ram size 6kbytes max. number of pages 24 max. number of packets 24 (fifos have 24 entries of 5 bits) max. pages per packet 6 page size 256 bytes 5.1 buffer memory the logical addresses for ram access are divided into tx area and rx area. the tx area is seen by the cpu as a window through which packets can be loaded into memory before queuing them in the tx fifo of packets. the tx area can also be used to examine the transmit completion status after packet transmission. the rx area is associated to the output of the rx fifo of packets, and is used to access receive packet data and status information. the logical address is specified by loading the addr ess pointer register. the pointer can automatically increment on accesses. all accesses to the ram are done via i/o space. a bit in the address pointer also specifies if the address refers to the tx or rx area. in the tx area, the host cpu has access to the next transmit packet being prepared for transmission. in the rx area, it has access to the first re ceive packet not processed by the cpu yet. the fifo of packets, existing beneath the tx and rx areas, is managed by the mmu. the mmu dynamically allocates and releases memory to be used by the transmit and receive functions.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 21 rev. 03-28-07 datasheet page = 256 bytes physical memory tx packet number rx packet number mmu mmu 1536 tx area 1536 rx area 11-bit logical address pointer register rcv bit rcv vs. tx area selection figure 5.1 ? mapping and paging vs. receive and transmit area
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 22 smsc ds ? LAN91C96I datasheet b a b c status count data status count data packet #a packet #b packet number register tx fifo to csma linear address mmu mapping memory cpu side status count data packet #c tx completion fifo fifo ports register c figure 5.2 ? transmit queues and mapping
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 23 rev. 03-28-07 datasheet d e d e status count data status count data packet #d packet #e fifo ports register rx fifo from csma linear address mmu mapping memory cpu side figure 5.3 ? receive queues and mapping
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 24 smsc ds ? LAN91C96I datasheet figure 5.4 ? LAN91C96I internal block diagram with data path 8-16 bit bus interface unit arbiter dma mmu ethernet protocol handler (eph) twisted pair transceiver 6k byte sram wr fifo rd fifo control rx data tx data control control address data control control tx/rx fifo pointer tpi tpo control eeprom interface tx data rx data endec aui
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 25 rev. 03-28-07 datasheet t x f i f o t x c o m p l e t i o n f i f o p n r r x f i f o p a c k e t n u m be r t x ( p a c k e t n u m b e r r e g ) r c v p o i n t e r r e g i s t e r & c o u n t e r l o a d i n c r x f i f o r e a d p o i n t e r l a t c h p o i n t e r r e g i s t e r p a c k e t # a d d r e s s d m a d a t a c s m a / c d c p u / n l a n ( f r o m a r b i t e r ) l o g i c a l a d d r e s s p a c k e t # mmu p h y si c a l a d d r e s s d a t a a d d r e s s w r i t e r e g r e a d r e g w r i t e d a t a r a m d a t a r e g i s t e r ( f i f o s ) r e a d d a t a t / n r figure 5.5 ? logical address generation and relevant registers
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 26 smsc ds ? LAN91C96I datasheet table 5.1 - LAN91C96I address space signals used local bus on-chip depth width ethernet i/o space (1) niord/ niowr y y 16 locations 8 or 16 bits table 5.2 - bus transactions in local bus mode a0 nsbhe d0-7 d8-15 8 bit mode ((nen16=1) (16bit=0)) 0 x even byte - 1 x odd byte - 16 bit mode otherwise 0 0 even byte odd byte 0 1 even byte - 1 0 - odd byte 1 1 invalid cycle 16bit: configuration register bit 7 iois8: csr register bit 5 nen16: pin nen16 8 bit mode: ((iois8 = 1) + (nmis16 = 1) 5.2 interrupt structure the ethernet interrupt is concept ually equivalent to the lan91c 94 interrupt line, it is the or function of all enabled interrupts within the ethernet core. the enabl ing, reporting, and clearing of these sources is controlled by the ecor register. the interrupt structur e is similar for local bus modes with the following exceptions: table 5.3 ? interrupt merging function local bus mode interrupt output intr0-3 ethernet interrupt source or function of all interrupt bits specif ied in the interrupt status register anded with their respective enable bits ethernet interrupt enable not applicable in local bus mode ethernet interrupt status bit intr bit in ecsr
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 27 rev. 03-28-07 datasheet 5.3 reset logic the pins and bits involved in the different reset mechanisms are: reset - input pin sreset - soft reset bit in ecor, or the sreset bit soft rst - eph soft reset bit in rcr table 5.4 ? reset logic resets the following functions samples local bus mode triggers eeprom read reset pin all internal logic yes yes ecor register sreset bit the ethernet controller function except for the bit itself. setting this bit also lowers the nireq/ready line. when cleared, the nireq/ready line is raised. no yes soft rst the ethernet controller itself except for the ia, conf and base registers. no no 5.4 power down logic states tables table 5.5 and table 5.6 describe the power do wn states of the LAN91C96I. the pins and bits involved in power down are: 1. pwrdwn/txclk - input pin valid when xendec is not zero (0). 2. pwrdwn bits in ecsr 3. enable function bit in ecor 4. pwrdn - legacy power down bit in control register.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 28 smsc ds ? LAN91C96I datasheet LAN91C96I power down states table 5.5 - local bus mode defined states (refer to table 5.6 for next states to wake-up events) current state no. pwrdwn pin (a= assrtd) ecor function enable ecsr power down ctr pwrdwn bit ctr wakeup_en bit powers down does not power down 1 a x x x x everything. asserts the modem power down pin (npwdn) also 2 na x 0 0 0 ethernet tx, rx, link 3 na x 0 0 1 ethernet tx ethernet rx, link 4 na x 0 1 1 ethernet tx, rx, link 5 na x 0 1 0 ethernet tx, rx, link notes: ? the chart assumes that ecor function enable bit is meaningless in local bus mode. ? ecsr power down bit must not be set to one(1) in local bus mode. table 5.6 - local bus mode next state no. wakes up by pwr dwn pin (a=assrtd) ecor fucntion enable ecsr power down ctr pwr- dwn bit ctr wakeup _en bit comments 1 pwrdwn pin deassertion na no change no change no change no change ecor function enable bit value is meaningless in local bus mode 2 na x 0 0 0 fully awake 3 by writing a 0 to ctr wakeup_en bit na x 0 0 0 4 by writing a 0 to ctr wakeup_en bit and ctr pwrdwn bit = 0 na x 0 0 0 the ctr pwrdwn bit has precedence unlike the lan91c95 5 by writing 0 to ctr pwrdwn bit na x 0 0 0 notes: ? the chart assumes that ecor function enable bit is meaningless in local bus mode. ? ecsr power down bit must not be set to one (1) in local bus mode.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 29 rev. 03-28-07 datasheet chapter 6 packet format in buffer memory for ethernet the packet format in memory is similar to that in the transmit and receive areas. the first word is reserved for the status word, the next word is used to s pecify the total number of bytes, and that in turn is followed by the data area. the data area holds the packet itself, and its length is determined by the byte count. the packet memory format is word oriented. figure 6.1 ? data packet format transmit packet receive packet status word written by csma upon transmit completion (see status register) written by csma upon receive completion (see rx frame status word) byte count written by cpu written by csma data area written/modified by cpu written by csma control byte written by cpu to control odd/even data bytes written by csma. also has odd/even bit reserved byte count (always even) status word data area last data byte (if odd) bit0 bit15 ram offset (decimal) 0 2 4 1534 max control byte last byte 1st byte 2nd byte
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 30 smsc ds ? LAN91C96I datasheet byte count divided by two, it defines the total number of words, including the stat us word, the byte count word, the data area and the control byte. the receive byte count always appears as even, the oddfrm bit of the re ceive status word indicates if the low byte of the last word is relevant. the trans mit byte count least significant bit will be assumed 0 by the controller regardless of the value written in memo ry. the maximum size of the frame can be stored in 6 pages (256 bytes per page), the maximum byte count number is 1536. data area (in ram) the data area starts at offs et 4 of the packet structur e, and it can extend for up to 1531 bytes. the data area contains six bytes of destination address followed by six bytes of source address, followed by a variable length number of bytes. on transmit, all bytes are provided by the cpu, including the source address. the LAN91C96I does not insert its own source address. on receive, all bytes are provided by the csma side. the 802.3 frame length word (frame type in ethernet ) is not interpreted by the LAN91C96I. it is treated transparently as data for both transmit and receive operations. control byte (in ram) the control byte always resides on the high byte of the last word. for transmit packets the control byte is written by the cpu as: x x odd crc 0 0 0 0 odd - if set, indicates an odd number of bytes, with the last byte being right before the control byte. if clear, the number of data bytes is even and the by te before the control by te is not transmitted. crc - when set, crc will be appended to the frame. this bit has only meaning if the nocrc bit in the tcr is set. for receive packets the control byte is written by the controller as: 0 1 odd 0 0 0 0 0 odd - if set, indicates an odd number of bytes, with the last byte being right before the control byte. if clear, the number of data bytes is even and the by te before the control byte should be ignored. receive frame status word (in ram) this word is written at the beginning of each receive frame in memory. it is not available as a register. algn err brod cast badcrc oddfrm tooln g too sho rt hash value mult cast 5 4 3 2 1 0
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 31 rev. 03-28-07 datasheet algnerr - frame had alignment error. brodcast - receive frame was broadcast. badcrc - frame had crc error. oddfrm - this bit when set indicates that the received frame had an odd number of bytes. toolng - the received frame is longer than the 802.3 maximum size (1518 bytes on the cable). tooshort - the received frame is shorter than t he 802.3 minimum size (64 bytes on the cable). hash value - provides the hash value used to index the multicast registers. can be used by receive routines to speed up the group address search. the has h value consists of the six most significant bits of the crc calculated on the destination a ddress, and maps into the 64 bit mult icast table. bits 5,4,3 of the hash value select a byte of the multicast table, while bi ts 2,1,0 determine the bit within the byte selected. examples of the address mapping are shown in the table below: address hash value 5-0 multicast table bit ed 00 00 00 00 00 0d 00 00 00 00 00 01 00 00 00 00 00 2f 00 00 00 00 00 000 000 010 000 100 111 111 111 mt-0 bit 0 mt-2 bit 0 mt-4 bit 7 mt-7 bit 7 multcast - receive frame was multicast. if hash value corresponds to a multicast table bit that is set, and the address was a multicast, the packet will pass addre ss filtering regardless of other filtering criteria.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 32 smsc ds ? LAN91C96I datasheet chapter 7 registers map in i/o space figure 7.1 - LAN91C96I registers bank0 bank1 bank2 bank3 0 2 4 6 8 a c e tcr eph status rcr counter mir mcr bank select register config base (individual address) general purpose control mmu command pnr arr fifo ports pointer data data interrupt multicast ta b l e non volatile, stored in eeprom. bank2 register used during run time. 16 bit registers 16 bit registers 16 bit registers 16 bit registers reserved mgmt revision ercv bank4 16 bit registers ecor (low byte) ecsr (high byte) bank select ia 0-1 ia 2-3 ia 4-5
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 33 rev. 03-28-07 datasheet 7.1 i/o space access the address is determined by t he ethernet i/o base registers . the ethernet i/o space can be conf igured as an 8 or 16 bit i/o space, and is similar to the la n91c94, lan91c 92, etc. i/o space mapping. to limit the i/o space requirements to 16 locati ons, the registers are split into 4 banks in local bus mode. the last word of the i/o area is shared by all banks and can be used to change the bank in use. banks 0 through 3 functionally correspond to the lan91c94 banks. registers are described using the following convention: offset name type symbol e bank select register read/write bsr bit 15 bit14 bit 13 bit 12 bit 11 bit 10 bit9 bit8 rst val rst val rst val rst val rst val rst val rst val rst val bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rst val rst val rst val rst val rst val rst val rst val rst val offset - defines the address offset within the io base where the register can be accessed at, provided the bank select has the appropriate va lue. the offset specifies the addre ss of the even byte (bits 0-7) or the address of the complete word. the odd byte can be accessed using address (offset + 1). some registers (e.g. the interrupt ack. or the interrupt mask) are functionally described as two eight bit registers. in such case, the offset of each one is independently specified. regardless of the functional description, when the la n91c96i is in 16 bit mode, all registers can be accessed as words or bytes. rst val - the default bit values upon hard reset are highlighted below each register.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 34 smsc ds ? LAN91C96I datasheet 7.2 i/o space registers description 7.2.1 bank select register offset name type symbol # in hex bank select register read/write bsr 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 bs2 bs1 bs0 x x x x x 0 0 0 bs2, bs1, bs0 - determine the bank presently in use. this register is always accessible except in power down mode and is used to select the register bank in use. the upper byte always reads as 33h and can be used to help determine the i/o location of the LAN91C96I. the bank select register is always acce ssible regardless of the value of bs0-2. accesses to non-existing banks will ignore writes and reads will return 0x33 on byte reads. bs2 bs1 bs0 bank # 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x 0 1 2 3 none i/o space - bank0 offset name type symbol 0 transmit control regi ster read/write tcr this register holds bits programmed by the cpu to control some of the protocol transmit options. fdse eten- type eph loop stp sqet fduplx mon_ csn nocrc 0 0 0 0 0 0 x 0 pad_en txp_en forcol loop txena 0 x x x 0 0 0 0 nocrc - does not append crc to transmitted frames when set, allows software to insert the desired crc. defaults to zero, namely crc inserted.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 35 rev. 03-28-07 datasheet fdse - full duplex switched ethernet. when set, the LAN91C96I is configured for full duplex switched ethernet, it defaults clear to normal csma/cd pr otocol. in fdse mode the LAN91C96I transmit and receive processes are fully independent, namely no defer ral and no collision detection are implemented. when fdse is set, fduplx is internally assumed high and mon_csn is assumed low regardless of their actual values. eten-type - early transmit underrun fu nction type. when low, eten bit in the ptr regist er will enable the early transmit underrun function as it was impl emented in the lan91c94. i.e. ?the early transmit function allows the cpu to enqueue the first transmit packet before it is fully loaded in packet memory. the loading operation proceeds in parallel with the tr ansmission, and in the case that the transmitter gets ahead of the cpu, the LAN91C96I wi ll prevent the transmission of erroneous data by forcing an underrun condition. underruns will be triggered by starving th e transmit dma if the LAN91C96I detects that the dma tx address exceeds the pointer address.? with eten-type set to one (1), eten bit set to one( 1) in the pointer register will mean the following: ?for underrun detection purposes the ram logica l address and packet numbers of the packet being loaded are compared against the logical address and packet numbers of the packet being transmitted. if the packet numbers match and the logical address of the packet being transmitted exceeds the address being loaded, the LAN91C96I will prevent the transmission of erroneous data by forcing an underrun condition. underruns will be triggered by starving th e transmit dma if the LAN91C96I detects that the dma tx address exceeds the pointer address.? note: the bit may be available for chips with rev. id 6 only and may be assigned to a different function in the future. eph_loop - internal loopback at the eph block. does not exercise the encoder decoder. serial data is looped back when set. defaults low. note: after exiting the loopback test, an sreset in the ecor or the soft_rst in the rcr must be set befor e returning to normal operation. stp_sqet - stop transmission on sqet error. if set, stops and disables transmitter on sqe test error. does not stop on sqet error and transmits next frame if clear. defaults low. fduplx - when set it enables full duplex operation. th is will cause frames to be received if they pass the address filter regardless of the source for the frame. when clear the node will not receive a frame sourced by itself. clearing this bit (normal operation), allows in promiscuous mode, not to receive it?s own packet. txp_en - this bit is reserved and should always be set to 0 on the LAN91C96I. mon_csn - when set the LAN91C96I monitors carrier while transmitting. it must see its own carrier by the end of the preamble. if it is not seen, or if carrier is lost during transmission, the transmitter aborts the frame without crc and turns itself off. when this bit is clear the transmitter ignores its own carrier. defaults low. pad_en - when set, the lan91c96 will pad transmit frames shorter than 64 bytes with 00. for tx, cpu should write the actual byte count before padded by the lan91c96 to the buffer ram, excludes the padded 00. when this bit is cleared, the lan91c96 does not pad frames. forcol - when set the transmitter will force a collision by not deferring deliberately. after the collision this bit is reset automatically. this bit defaults low to normal operation. loop - local loopback. when set, transmit frames are internally looped to the receiver after the encoder/decoder. collision and carrier sense are ignor ed. no data is sent out. defaults low to normal mode.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 36 smsc ds ? LAN91C96I datasheet txena - transmit enabled when set. transmit is disabled if clear. when the bit is cleared the LAN91C96I will complete the current transmission before stoppi ng. when stopping due to an error, this bit is automatically cleared. table 7.1 - transmit loop aui fds e fduplx eph_loop loop loops at transmits to network x x x 1 x eph block no x x 1 0 1 endec no 1 0 1 0 0 cable yes 0 0 1 0 0 10base-t driver yes x 0 0 0 0 normal csma/cd - no loopback yes x 1 1 0 0 full duplex switched ethernet - no loopback and no sqet yes i/o space - bank0 offset name type symbol 2 eph status register read only ephsr this register stores the st atus of the last transmitted frame. this register value, upon individual transmit packet completion, is stored as the first word in th e memory area allocated to the packet. packet interrupt processing should use the copy in memory as the re gister itself will be updated by subsequent packet transmissions. the register can be used for real time values (like txena and link ok). if txena is cleared the register holds the last packet completion status. tx unrn link_ ok res ctr _rol exc _def lost carr latcol wakeup 0 0 0 0 0 0 0 0 tx defr ltx brd sqet 16col ltx mult mul col sngl col tx_suc 0 0 0 0 0 0 0 0 txunrn - transmit under run. set if under run occurs, it also clears txena bit in tcr. cleared by setting txena high. this bit should never be set under normal operation. link_ok - state of the 10base-t link integrity test. a transition on th e value of this bit generates an interrupt when the le enable bit in the control register is set. res ? this bit is reserved and will always return a zero(0). ctr_rol - counter roll over. when set one or more 4 bit counters have reached maximum c ount (15). cleared by reading the ecr register. exc_def - excessive deferral. when set last/current transmit was deferred for more than 1518 * 2 byte times. cleared at the end of every packet sent. lost_carr - lost carrier sense. when set indicate s that carrier sense was not present at end of preamble. valid only if mon_csn is enabled. this condition causes txena bit in tcr to be reset. cleared by setting txena bit in tcr.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 37 rev. 03-28-07 datasheet latcol - late collision detected on la st transmit frame. if set a late collision was detected (later than 64 byte times into the frame). when detected the transmitter jams and turns itself off clearing the txena bit in tcr. cleared by setting txena in tcr. wakeup - when this bit is set, it indicates that a re ceive packet was received that had the ?magic? packet (mp) signature of the node?s own individual address repetitions in it. this bit indicates a valid detection for magic packet. tx_defr - transmit deferred. when set, carrier was detec ted during the first 6.4 usec of the inter frame gap. cleared at the end of every packet sent. ltx_brd - last transmit frame was a broadcast. set if frame was broadcast. cleared at the start of every transmit frame. sqet - signal quality error test. the transmitter opens a 1.6 us window 0.8 us after transmission is completed and the receiver returns inactive. during th is window, the transmitter expects to see the sqet signal from the transceiver. the absence of this signal is a 'signal quality error' and is reported in this status bit. transmission stops and eph int is set if st p_sqet is in the tcr is also set when sqet is set. this bit is cleared by setting txena high. 16col - 16 collisions reached. set when 16 collisions are detected for a transmit frame. txena bit in tcr is reset. cleared when txena is set high. ltx_mult - last transmit frame was a multicast. set if frame was a multicast. cleared at the start of every transmit frame. mulcol - multiple collision detected for the last tr ansmit frame. set when more than one collision was experienced. cleared when tx_suc is high at the end of the packet being sent. snglcol - single collision detected for the last transmi t frame. set when a collision is detected. cleared when tx_suc is high at the end of the packet being sent. tx_suc - last transmit was successful. set if transmit comp letes without a fatal error. this bit is cleared by the start of a new frame transmission or when txena is set high. fatal errors are: ? 16 collisions ? sqet fail and stp_sqet = 1 ? fifo underrun ? carrier lost and mon_csn = 1 ? late collision
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 38 smsc ds ? LAN91C96I datasheet i/o space - bank0 offset name type symbol 4 receive control register read/write rcr soft rst filt car 0 0 0 0 strip crc rxen 0 0 0 0 0 0 0 0 almul prms rx_ abort 0 0 0 0 0 0 0 0
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 39 rev. 03-28-07 datasheet soft_rst - software activated reset. active high. in itiated by writing this bit high and terminated by writing the bit low. the LAN91C96I configuration is not preserved, except for co nfiguration, base, and ia0- 5 registers. the eeprom in local bus mode is not reloaded after software reset. filt_car - filter carrier. when set filters leading e dge of carrier sense for 12 bit times. otherwise recognizes a receive frame as soon as carrier sense is active. strip_crc - when set it strips the crc on received frames. when clear the crc is stored in memory following the packet. defaults low. rxen - enables the receiver when set. if cleared, completes receiving current frame and then goes idle. defaults low on reset. almul - when set accepts all multicast frames (frame s in which the first bit of da is '1'). when clear accepts only the multicast frames that matc h the multicast table setting. defaults low. prms - promiscuous mode. when set receives all frames. change vs. lan91c92: does not receive its own transmission when not in full duplex(fduplx)!. rx_abort - this bit is set if a receive frame was aborted due to length longer than 1532 bytes. the frame will not be received. the bit is cleared by reset or by the cpu writing it low. i/o space - bank0 offset name type symbol 6 counter register read only ecr counts four parameters for mac statistics. when an y counter reaches 15 an interrupt is issued. all counters are cleared when reading the register, and do not wrap around beyond 15. number of exc. deferred tx number of deferred tx 0 0 0 0 0 0 0 0 multiple collision count single collision count 0 0 0 0 0 0 0 0 each four bit counter is increment ed every time the corresponding event, as defined in the eph status register bit description, occurs. note that the count ers can only increment once per enqueued transmit packet, never faster, limiting the rate of interrupts that can be generated by the counters. for example if a packet is successfully transmitted after one collision the single collision count field is incremented by one. if a packet experiences between 2 to 16 collisions, the multiple collision count field is incremented by one. if a packet experiences deferral the number of deferred tx field is incremented by one, even if the packet experienced multiple deferrals during its collision retries. the counter register facilitates maintaining statistics in the auto release mode where no transmit interrupts are generated on successful transmissions. reading the register in the transmit service routine will be enough to maintain statistics.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 40 smsc ds ? LAN91C96I datasheet i/o space - bank0 offset name type symbol 8 memory information register read only mir for software compatibility with other lan9000 parts a ll memory-related information is represented in 256 x m byte units, where the multiplier m is dete rmined by the mcr upper byte. m equals ?1? for the LAN91C96I. free memory available (in bytes* 256* m) 0 0 0 1 1 0 0 0 memory size (in bytes* 256* m) 0 0 0 1 1 0 0 0 free memory available - this register can be read at any time to determine the amount of free memory. the register defaults to the memory size upon reset or upon the reset mmu command. memory size - this register can be read to determi ne the total memory size, and will always read 18h (6144 bytes) for the LAN91C96I. memory size register m actual memory lan91c90 ffh 1 64 kbytes lan91c90 40h 1 16 kbytes lan91c92/ lan91c94 12h 1 4608 bytes lan91c95 18h 1 6144 bytes LAN91C96I 18h 1 6144 bytes lan91c100 ffh 2 128 kbytes i/o space - bank0 offset name type symbol a memory configuration register lower byte read/write upper byte read only mcr memory size multiplier ?m? 0 0 1 1 0 0 1 1 memory reserved for transmit (in bytes * 256 * m) 0 0 0 0 0 0 0 0 memory reserved for transmit - programming th is value allows the host cpu to reserve memory to be used later for transmit, limiting the amount of memory that receive packets can use up. when programmed for zero, the memory allocation betw een transmit and receive is completely dynamic. when programmed for a non-zero value, the alloca tion is dynamic if the free memory exceeds the programmed value, while receive allocation requests are denied if the free memory is less or equal to the programmed value. this register defaults to zero upon reset. it is not affected by the reset mmu command. the value written to the mcr is a reserved memory space in addition to any memory currently in use. if the memory allocated for transmi t plus the reserved space for transmit is required to be constant (rather than grow with transmit allocati ons) the cpu should update the value of this register after allocating or releasing memory.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 41 rev. 03-28-07 datasheet the contents of mir as well as the low byte of mcr are specified in 256* m bytes. the multiplier m is determined by bits 11, 10 and 9 as follows: device bit 11 bit 10 bit 9 m max memory size feast 0 1 0 2 256 ( note 7.1 ) 256 ( note 7.1 ) 2=128k lan91c90 0 0 1 1 256 ( note 7.1 ) 256 ( note 7.1 ) 1=64k future 0 1 1 4 256k future 1 0 0 8 512k future 1 0 1 16 1m note 7.1 bits 11, 10 and 9 are read only bits used by the soft ware driver to transparently run on different controllers of the lan9000 family. i/o space - bank1 offset name type symbol 0 configuration register read/write cr the configuration register holds bits that define t he device configuration and are not expected to change during run-time. this register is part of t he eeprom saved setup in local bus mode only. 0 no wait full step set sqlch aui select 0 x x 0 x 0 0 0 16bit dis link reserved int sel1 int sel0 function of en16* pin 0 1 1 0 0 0 x no wait - when set, does not request additional wait states. an exception to this are accesses to the data register if not ready for a transfer. when clear , negates iochrdy for two to three 20mhz clocks on any cycle to the LAN91C96I. full step - this bit is used to select the signaling mode for the aui port. when set the aui port uses full step signaling. defaults low to half step signaling. this bit is only meaningful when aui select is high. set sqlch - when set, the squelch level used for th e 10base-t receive signal is 240mv. when clear the receive squelch level is 400mv. defaults low. aui select - when set the aui interface is used, when clear the 10base-t interface is used. defaults low. 16bit - used in conjunction with en16* and io is 8 to define the width of the system bus. if the en16* pin is low, this bit is forced high. otherwise the bi t defaults low and can be progr ammed by the host cpu. dis link - this bit is used to disable the 10base- t link test functions. when this bit is high the LAN91C96I disables link test functions by not generating nor monitoring the network for link pulses. in this mode the LAN91C96I will transmit packets regardless of the link test, the ephsr link_ok bit will be set and the link led will stay on. when low the link te st functions are enabled. if the link status indicates fail, the ephsr link_ok bit will be low, while tr ansmit packets enqueued will be processed by the LAN91C96I, transmit data will not be sent out to the cable.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 42 smsc ds ? LAN91C96I datasheet int sel1-0 - in local bus mode, used to select one out of four interrupt pins. the three unused interrupts are tristated. int sel1 int sel0 interrupt pin used 0 0 intr0 0 1 intr1 1 0 intr2 1 1 intr3 i/o space - bank1 offset name type symbol 2 base address register read/write bar for local bus mode only, this re gister holds the i/o address decode option chosen for the i/o and rom space. it is part of the eeprom saved setup, and is not usually modified during run-time. a15 a14 a13 a9 a8 a7 a6 a5 0 0 0 1 1 0 0 0 rom size ra18 ra17 ra16 ra15 ra14 0 1 1 0 0 1 1 1 a15 - a13 and a9 - a5 - these bits are compared in local bus mode against the i/o address on the bus to determine the iobase for LAN91C96I re gisters. the 64k i/o space is fu lly decoded by the LAN91C96I down to a 16 location space, therefore the unspeci fied address lines a4, a10, a11 and a12 must be all zeros. rom size - determines the rom decode area in local bus mode memory space as follows: 00 = rom disable 01 = 16k: ra14-18 define rom select. 10 = 32k: ra15-18 define rom select. 11 = 64k: ra16-18 define rom select. ra18-ra14 - these bits are compared in local bus mode against the memory address on the bus to determine if the rom is being accessed, as a f unction of the rom size. rom accesses are read only memory accesses defined by memrd* going low. for a full decode of the address space unspecified up per address lines have to be: a19 = "1", a20-a23 lines are not directly decoded, however local bus systems will only activate smemrd* only when a20- a23=0. all bits in this register are loaded from the serial eeprom in local bus mode only. the i/o base decode defaults to 300h (namely, the high byte defaults to 18h). rom size defaults to 01. rom decode defaults to cc000 (namely the low byte defaults to 67h). below chart shows t he decoding of i/o base address 300h:
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 43 rev. 03-28-07 datasheet a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 i/o space - bank1 offset name type symbol 4 through 9 individu al address registers read/write iar these registers are loaded starting at word lo cation 20h of the eeprom upon hardware reset or eeprom reload. the registers can be modified by the software driver, but a store operation will not modify the eeprom individual address contents. bit 0 of individual address 0 register corresp onds to the first bit of the address on the cable. address 0 0 0 0 0 0 0 0 0 address 1 0 0 0 0 0 0 0 0 address 2 0 0 0 0 0 0 0 0 address 3 0 0 0 0 0 0 0 0 address 4 0 0 0 0 0 0 0 0 address 5 0 0 0 0 0 0 0 0
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 44 smsc ds ? LAN91C96I datasheet i/o space - bank1 offset name type symbol a general address registers read/write gpr high data byte 0 0 0 0 0 0 0 0 low data byte 0 0 0 0 0 0 0 0 this register can be used as a way of storing and retrieving non-volatile information in the eeprom to be used by the software driver. the storage is word oriented, and the eeprom word address to be read or written is specified using the six lo west bits of the pointer register. this register can also be used to sequentially program the individual address area of the eeprom, that is normally protected from accidental store operations. this register will be used for eeprom read and write only when the eeprom select bit in the control register is set. this allows generic eeprom read and wr ite routines that do not affect the basic setup of the LAN91C96I. i/o space - bank1 offset name type symbol c control register read/write ctr 0 rcv_ bad pwrdn wakeup _en auto releas e 1 0 0 0 0 0 x x 1 le enable cr enable te enable eeprom select reload store 0 0 0 x x 0 0 0 rcv_bad - when set, bad crc packets are received. when clear bad crc packets do not generate interrupts and their memory is released. pwrdn - active high bit used to put the ethernet function in power down mode. cleared by: 1. a write to any register in the LAN91C96I i/o space. 2. hardware reset. this bit is combined with the pwrdwn bit in ecsr and with the powerdown bit to determine when the function is powered down. wakup_en - active high bit used to enable the contro ller in the appropriate power down modes to power up and set the wakeup bit in the ephsr -> generate an eph interrupt(if not masked). when clear (0), no ?magic packet? scanning is done on receive packets. note: setting (1) the bit is meaningful only if the functi on is enabled (enable function bit in cor; offset 8000h)
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 45 rev. 03-28-07 datasheet auto release - when set, transmit pages are released by transmit completion if the transmission was successful (when tx_suc is set). in that case there is no status word associated with its packet number, and successful packet numbers are not even written into the tx completion fifo. a sequence of transmit packets will only generate an interrupt when the sequence is completely transmitted (tx empty int will be set), or when a packet in the sequence experiences a fatal error (tx int will be set). upon a fatal error txena is cleared and the transmission sequence stops. the packet number that failed is the present in the fifo ports register, and its pages are not released, allowing the cpu to restart the sequence after corrective action is taken. le enable - link error enable. when set it enables th e link_ok bit transition as one of the interrupts merged into the eph int bi t. defaults low (disabled). writing this bit also serves as the acknowledge by clearing previous link interrupt conditions. cr enable - counter roll over enable. when set it en ables the ctr_rol bit as one of the interrupts merged into the eph int bi t. defaults low (disabled). te enable - transmit error enable. when set it enables transmit error as one of the interrupts merged into the eph int bit. defaults lo w (disabled). transmit error is any condition that clears txena with tx_suc staying low as described in the ephsr register. eeprom select - this bit allows the cpu to spec ify which registers the eeprom reload or store refers to. when high, the general purpose register is the only register read or written. when low, the reload and store functions are enabled. reload the LAN91C96I reads the configuration, base and individual address, and store writes the configuration and base registers. also when set it will read the eeprom and update relevant r egisters with its contents. this bit then clears upon completing the operation. store the store LAN91C96I bit when set, stores the contents of all relevant regist ers in the serial eeprom. this bit is cleared upon completing the operation. note: when an eeprom access is in progress the store and reload bits will be read back as high. the remaining 14 bits of this register will be invalid. du ring this time, attempted read/write operations, other than polling the eeprom status, will not have any effect on the internal registers. the cpu can resume accesses to the LAN91C96I after both bits are low. a worst case reload operation initiated by reset or by software takes less than 750usec in either mode.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 46 smsc ds ? LAN91C96I datasheet i/o space - bank2 offset name type symbol 0 mmu command register write only busy bit readable mmucr this register is used by the cpu to control the memo ry allocation, de-allocation, tx fifo and rx fifo control. the three command bits determine the command issued as described below: command 0 n2 n1 n0/ busy w x y z 0 command set: wxyz 0000 0) - noop - no operation - 0010 2) - allocate memory for tx - n2, n1, n0 defines the amount of memory requested as (value + 1) 256* bytes. namely n2, n1, n0 = 1 will request 2 256* = 512 bytes. valid range for n2, n1, n0 is 0 through 5. a shift-based divide by 256 of the packet length yields the appropriate value to be used as n2, n1 and n0. immediately generates a completion code at the allocation r esult register. can optionally generate an interrupt on successful completion. the allo cation time can take worst case (n2, n1, n0 + 2)* 200s. 0100 4) - reset mmu to initial state - free s all memory allocations, clears relevant interrupts, resets packet fifo pointers. 0110 6) - remove frame from top of rx fifo - to be issued after cpu has completed processing of present receive frame. this command removes the receive packet number from the rx fifo and brings the next receiv e frame (if any) to the rx area (output of rx fifo). 0111 7) - remove frame from top of tx fifo- to be issued only after the host disabled the transmitter and has completed processi ng of the present transmit frame. note : determining transmit completion is done by polling th e tempty bit in the transmit fifo port register. this command removes the transmit packet number fr om the tx fifo and brin gs the next transmit frame (if any) to the tx area (output of tx fifo). 1000 8) - remove and release top of rx fifo - li ke 6) but also releases all memory used by the packet presently at the rx fifo output. 1010 a) - release specific packet - frees all pag es allocated to the pa cket specified in the packet number register. should not be used for frames pending transmission. typically used to remove transmitted frames, after reading their completion status. can be used following 6 (to release receive packet memory in a more flexible way than 8). 1100 c) - enqueue packet number into tx fifo - this is the normal method of transmitting a packet just loaded into ram. the packet number to be enqueued is taken from the packet number register.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 47 rev. 03-28-07 datasheet 1110 f) - reset tx fifos - this command will re set both tx fifos. the tx fifo holding the packet numbers awaiting transmission and the tx completion fifo. this command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. the reset tx fifos command should only be used w hen the transmitter is di sabled. unlike the reset mmu command, the reset tx fifos does not release any memory. notes : ? only command 2 uses n2, n1 and n0. ? when using the reset tx fifos command, the cpu is re sponsible for releasing the memory associated with outstanding packets, or re-enqueuing them. packet numbers in the completion fifo can be read via the fifo ports register before issuing the command. ? mmu commands releasing memory (commands 8 and a) should only be issued if the corresponding packet number has memory allocated to it. command sequencing a second allocate command (command 2) should not be issued until the present one has completed. completion is determined by reading the failed bit of the allocation result register or through the allocation interrupt. a second release command (commands 8 and a) should not be issued if the previous one is still being processed. the busy bit indicates that a releas e command is in progress. after issuing command a, the contents of the pnr should not be changed until busy goes low. after issuing command 8, command 6 should not be issued until busy goes low. busy bit - readable at bit ?0? of the mmu command register address. when set indicates that mmu is still processing a release command. when clear, mmu has already completed last release command. busy and failed bits are set upon the trailing edge of command. i/o space - bank2 offset name type symbol 1 auto tx start register read/write autotx d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 auto tx start register - this register specifies the value, in 16 byte multiples of when the transmit state machine starts a transmit operation when th e associated transmit buffer is enqueued into the transmit fifo. the autotx bit as well as the eten bit must both be set in the pointer register in order for this register to be utilized. note: this register must be non-zero for t he auto-tx function to work. a value of ?0? will disable this function. the rcv bit in the pointer register must be zero (0) as well. the rcv bit must be cleared so that the packet being written and enqueued is being selected by the pnr and not the receive fifo. register operation: when early transmit is enabled vi a the eten bit in the pointer register, the host is able to enqueue a buffer for transmit operation befor e all of the transmitted data is copied into the LAN91C96I dual ported ram. in the case of the autotx bit being cleared, the host must manually start the transmit operation. when the autotx bit is set, the eph transmit engine compares the number of bytes moved into the transmit packet buffer with the value of the auto tx start register to start transmit operation. this eliminates t he requirement for the host to manually start the transmit.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 48 smsc ds ? LAN91C96I datasheet i/o space - bank2 offset name type symbol 2 packet number register read/write pnr reserved packet number at tx area 0 0 0 0 0 0 0 0 packet number at tx area - the value written into this register determines which packet number is accessible through the tx area. some mmu commands use the number stored in this register as the packet number parameter. this register is cl eared by a reset or a reset mmu command. reserved ? this bit is reserved. i/o space - bank2 offset name type symbol 3 allocation result register read only arr this register is updated upon an allocate memory mmu command. failed allocated packet number 1 0 0 0 0 0 0 0 failed - a ?0? indicates a successful allocation completion. if the allocation fails th e bit is set and only cleared when the pending allocation is satisfied. defaults high upon reset and reset mmu command. for polling purposes, the alloc_int in the interrupt status register should be used because it is synchronized to the read operation. sequence: 1. allocate command 2. poll alloc_int bit until set 3. read allocation result register allocated packet number - packet number associated wi th the last memory al location request. the value is only valid if the failed bit is clear. note: for software compatibility with future versions, the value read from the arr after an allocation request is intended to be written into the pnr as is, with out masking higher bits (provided failed = ?0?).
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 49 rev. 03-28-07 datasheet i/o space - bank2 offset name type symbol 4 fifo ports register read only fifo this register provides access to the read ports of the receive fifo and the transmit completion fifo. the packet numbers to be processed by the interrupt service routines are read from this register. rempty rx fifo packet number 1 0 0 0 0 0 0 0 tempty tx fifo packet number 1 0 0 0 0 0 0 0 rempty - no receive packets queued in the rx fifo. for polling purposes, uses the rcv_int bit in the interrupt status register. top of rx fifo packet number - packet number present ly at the output of the rx fifo. only valid if rempty is clear. the packet is removed from the rx fifo using mmu commands 6) or 8). tempty - no transmit packets in completion queue. for polling purposes, uses the tx_int bit in the interrupt status register. tx fifo packet number - packet number presently at the output of the tx fifo. only valid if tempty is clear. the packet is removed when a tx int acknowledge is issued. note : for software compatibility with futu re versions, the value read from each fifo register is intended to be written into the pnr as is, without masking higher bits (provided tempty and rempty = 0 respectively). i/o space - bank2 offset name type symbol 6 pointer register read/write ptr rcv auto incr. read eten autotx pointer high 0 0 0 0 0 0 0 0 pointer low 0 0 0 0 0 0 0 0 pointer register - the value of this register de termines the address to be accessed within the transmit or receive areas. it will auto-increment on acce sses to the data register when auto incr. is set. the increment is by one for every byte access, and by two for every word access. when rcv is set the address refers to the receive area and uses the output of rx fifo as the packet number, when rcv is clear the address refers to the transmit area and uses the packet number at the packet number register. read bit - determines the type of access to follow. if the read bit is high the operation intended is a read. if the read bit is low the oper ation is a write. loading a new pointer value, with the read bit high, generates a pre-fetch into the data register for read purposes. read-back of the pointer will indicate the value of the address last accessed by the cpu (rather than the last pre-fetched). this allows any in terrupt routine that uses the pointer, to save it and restore it without affecting the process being interrupted. the pointer register should not be loaded until 400ns after the last write operation to the data register to ensure that the data register fifo is empty. on r eads, if iochrdy is not connected to the host, the data
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 50 smsc ds ? LAN91C96I datasheet register should not be read before 400ns after the pointer was loaded to allow the data register fifo to fill. if the pointer is loaded using 8 bit writes, the low byte should be loaded first and the high byte last. eten bit - when set enables early transmit underrun detection. normal operation when clear. if tcr bit 14 (eten-type) is zero and this bit is se t, the early transmit underr un function will be enabled as it was implemented in the lan91c94: "the early transmit function allows the cpu to enqueue the first transmit packet before it is fully loaded in packet memory. the loading operation proceeds in paralle l with the transmission, and in the case that the transmitter gets ahead of the cpu, the lan91c94 wi ll prevent the transmission of erroneous data by forcing an underrun condition. underruns will be tr iggered by starving the trans mit dma if the LAN91C96I detects that the dma tx address exceeds the pointer address.? if tcr bit 14 (eten-type) is zero and this bit is set, the early transmit und errun function defined as follows: ?for underrun detection purposes the ram logical address and packet numbers of the packet being loaded are compared against the logical address and packet numbers of the packet being transmitted. if the packet numbers match and the logical address of the packet being transmitted exceeds the address being loaded the LAN91C96I will prevent the transmission of erroneous data by forcing an underrun condition. underruns will be triggered by starving t he transmit dma if the LAN91C96I detects that the dma tx address exceeds the pointer address.? note: eten-type (bit 14) in tcr may be implemented for re v. id 6 only. in the absence of eten-type in tcr, eten will have the definiti on as eten-type were clear only. autotx bit - when set, enables the transmit state mach ine to automatically start a transmit operation with no host intervention determined by the number of bytes being copied into the transmit buffer enqueued in the transmit fifo. the eten bit must also be set in order for this function to be enabled and the rcv bit must be cleared (0). when the auto tx bit is cl eared, the transmit state machine must manually be enabled to enqueue a transmit buffer. if auto incr. is not set, the pointer must be loaded with an even value. i/o space - bank2 offset name type symbol 8 & a data register read/write data data high data low data register - used to read or write the data buffer byte/word presently addressed by the pointer register.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 51 rev. 03-28-07 datasheet this register is mapped into two uni-directional fifo s that allow moving words to and from the LAN91C96I regardless of whether the pointer address is even or odd. data goes through the write fifo into memory, and is pre-fetched from memory into the read fifo. if byte accesses are used, the appropriate (next) byte can be accessed through the data low or data high registers. the order to and from the fifo is preserved. byte and word accesses can be mixed on the fly in any order. this register is mapped into two consecutive word lo cations to facilitate the usage of double word move instructions. the data register is accessible at an y address in the 8 through ah range, while the number of bytes being transferred are determined by a0 and nsbhe in local bus mode. i/o space - bank2 offset name type symbol c interrupt status register read only ist tx idle int ercv int eph int rx_ ovrn int alloc int tx empty int tx int rcv int 0 0 0 0 0 1 0 0 offset name type symbol c interrupt acknowledge register write only ack ercv int rx_ ovrn int tx empty int tx int offset name type symbol d interrupt mask register read/write msk tx idle int mask ercv int mask eph int mask rx_ ovrn int mask alloc int mask tx empty int mask tx int mask rcv int mask 0 0 0 0 0 0 0 0 this register can be read and written as a word or as two individual bytes. the interrupt mask register bits enable the appropria te bits when high and disable them when low. a mask bit being set will cause a hardware interrupt. tx idle int - transmit idle interrupt. set when the trans mit state machine is not active. this bit is used under the condition where the tx fifo is still not empt y, the transmitter is disabled and the host wants to determine when the transmitter is completed with the current transmit packet. this event usually happens when the host wants to insert at the head of the transmit queue a frame for example. typical flow of events/condition: 1. the transmit fifo is not empty 2. the transmit done fifo is either empty or not empty
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 52 smsc ds ? LAN91C96I datasheet 3. the transmit engine is either active or not active flow of events for an insertion of a transmit packet: 1. disable the transmitter 2. remove and release any ?transmit done? packets in the tx fifo 3. via polling or an interrupt driven event, determine stat us of tx idle int bit and wait until this bit is set. this will determine when the transmitter is truly done with all transmit events. 4. remove and store (if any, in software) packet numbers from the transmit fifo. (these packets will later be restored into the tx fifo after the control frame is inserted into the front of the tx fifo). 5. enable transmitter 6. en-queue packe t into tx fifo 7. en-queue rest of packets, if an y, into tx fifo (restore tx fifo) ercv int - early receive interrupt. set whenever a receive packet is being received, and the number of bytes received into memo ry exceeds the value programmed as e rcv threshold (bank 3, offset ch). ercv int stays set until acknowledged by writi ng the interrupt acknowledge register with the ercv int bit set. eph int - set when the ethernet protocol handler se ction indicates one out of various possible special conditions. this bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level drivers. the exact nature of the interrupt can be obtained from the eph status register (ephsr), and enabl ing of these sources can be done via the control register. the possible sources are: 1. link - link test transition 2. ctr_rol - statistics counter roll over 3. txena cleared - a fatal transmit error occurred forcing txena to be cleared. tx_suc will be low and the specific reason will be reflected by the bits: 3.1 txunrn - transmit under-run 3.2 sqet - sqe error 3.3 lost carr - lost carrier 3.4 latcol - late collision 3.5 16col - 16 collisions any of the above interrupt sources can be masked by the appropriate enable bits in the control register. 1) le enable (link error enable), 2) cr enable (counter roll over), 3) te enable (transmit error enable) eph int will only be cleared by the following methods: 1. clearing the le enable bit in the control regist er if an eph interrupt is caused by a link_ok transition.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 53 rev. 03-28-07 datasheet 2. reading the counter register if an eph interr upt is caused by statistics counter roll over. 3. setting txena bit high if an eph interrupt is caused by any of the fatal transmit error listed above (3.1 to 3.5). rx_ovrn int - set when 1) the receiver aborts due to an overrun due to a failed memory allocation, 2) the receiver aborts due to a packet length of greater th an 2k bytes, or 3) the receiver aborts due to the rcv discrd bit in the ercv register set. the rx_ovr n int bit latches the condition for the purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge register with the rx_ovrn int bit set. alloc int - set when an mmu request for tx ram pages is successful. this bit is the complement of the failed bit in the allocation result register. the alloc int bit is cleared by the mmu when the next allocation request is processed or allocation fails. tx empty int - set if the tx fifo goes empty, can be used to generate a single interrupt at the end of a sequence of packets enqueued for transmission. this bi t latches the empty condition, and the bit will stay set until it is specifically cleared by writing the acknowledge register wi th the tx empty int bit set. if a real time reading of the fifo empty is desired , the bit should be first cleared and then read. the tx_empty mask bit should only be set after the following steps: a) a packet is enqueued for transmission b) the previous empty condition is cleared (acknowledged) tx int - set when at least one pa cket transmission was completed or any of the below transmit fatal errors occurs: 1. txunrn - transmit under-run 2. sqet - sqe error 3. lost carr - lost carrier 4. latcol - late collision 5. 16col - 16 collisions the first packet number to be serviced can be read from the fifo ports register. the tx int bit is always the logic complement of the tempty bit in the fifo ports register. after servicing a packet number, its tx int interrupt is removed by writing th e interrupt acknowledge register with the tx int bit set. rcv int - set when a receive interrupt is generated. the first packet number to be serviced can be read from the fifo ports register. the rcv int bit is alwa ys the logic complement of the rempty bit in the fifo ports register. receive interrupt is cleared when rx fifo is empty. note: for edge triggered systems, the interrupt service r outine should clear the interrupt mask register, and only enable the appropriate interrupts after the interrupt source is serviced (acknowledged).
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 54 smsc ds ? LAN91C96I datasheet 5 4 3 2 1 0 5 4 3 2 1 0 i n t e r r u p t s t at u s r e g i s t e r i n t e r r u pt m a s k r e g i s t e r o e n o e n r d i st 1 6 d a t a b u s d 0 - 7 d 8 - 1 5 e d g e d e t e c t o r o n l i n k er r l em a s k c t r - r o l c r m a sk t e m a s k t x en a t x _ s v c e ph sr i n t e r r u p t s m e r g e d i n t o e p h i n t i n t a c k 2 i n t a c k 4 d s q n q t x f i f o em pt y d s q n q r x _ o v r n a l l o c a t i o n f a i l e d r c v f i f o n o t e m p t y r c v i n t t x i n t t x e m p t y i n t a l l o c i n t r x _ o v r n i n t e p h i n t i n t m a i n i n t e r r u p t s e r c v i n t 6 6 7 7 t x id l e in t t x c o m p l e t e f a t a l t r a n s m i t e r r o r i n t a c k 1 d s q n q n w r a c k d s q n q ercv i n t a c k 6 t x u n r n s q e t l o s t c a r r l at c o l 1 6 c o l t x st a t e m a c h i n e i s n o t a c t i v e figure 7.2 ? interrupt structure
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 55 rev. 03-28-07 datasheet i/o space - bank 3 offset name type symbol 0 through 7 multicast table read/write mt multicast table 0 0 0 0 0 0 0 0 0 multicast table 1 0 0 0 0 0 0 0 0 multicast table 2 0 0 0 0 0 0 0 0 multicast table 3 0 0 0 0 0 0 0 0 multicast table 4 0 0 0 0 0 0 0 0 multicast table 5 0 0 0 0 0 0 0 0 multicast table 6 0 0 0 0 0 0 0 0 multicast table 7 0 0 0 0 0 0 0 0 the 64 bit multicast table is used for group address fi ltering. the hash value is defined as the six most significant bits of the crc of t he destination addresses. the three ms b's determine the register to be used (mt0-7), while the other three determine the bit within t he register. if the appropriate bit in the table is set, the packet is received. if the almul bit in the rcr register is set, all multicas t addresses are received regardless of the multicast table values. hashing is for a partial group address filt ering scheme. additional filtering is done in software. but the hash value being a part of the receive status word, the receive routine can reduce the search time significantly. with the proper memory structure, t he search is limited to comparing only the multicast addresses that have the actual hash value in question. i/o space - bank3 offset name type symbol 8 management interface read/write mgmt this register contains status bits and control bits for management of different transceivers modules. some of the pins are shared with the serial eeprom interf ace. management is software controlled, and does not use the serial eeprom and the transceiver management functions at the same time. nxndec ios2 ios1 ios0 0 0 1 1 mdoe mclk mdi md0 0 0 1 1 0 0 0 0 nxndec - read only bit reflecting t he status of the nxendec pin. ios0-2 - read only bits reflecting the status of the ios0-2 pins. mdo - the value of this bit drives the eedo pin when mdoe=1.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 56 smsc ds ? LAN91C96I datasheet mdclk - the value of this bit drives the eesk pin when mdoe=1. mdoe - when this bit is high pins eedo eecs an d eesk will be used for transceiver management functions, otherwise the pins assume the eeprom values. mode=0 mode=1 eedo serial eeprom data out bit mdo eesk serial eeprom clock bit mclk eecs serial eeprom chip select 0 i/o space - bank3 offset name type symbol a revision register read only rev 0 0 1 1 0 0 1 1 chip rev 0 1 0 0 1 0 0 1 chip id value device 3 lan91c90/lan91c92 4 lan91c94 5 lan91c95 4* LAN91C96I 7 lan91c100 8 lan91c100fd 9 lan91c110 chip - chip id. can be used by software drivers to identify the device used. rev - revision id. incremented for each revision of a given device. note: the LAN91C96I shares the same chip id (#4) as the lan91c94. the rev. id for the LAN91C96I will begin from six (#6).
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 57 rev. 03-28-07 datasheet i/o space - bank3 offset name type symbol c early rcv register read/write ercv rcv counter 0 0 1 1 0 0 1 1 rcv discrd ercv threshold 0 0 0 1 1 1 1 1 rcv discrd - set to discard a packet being received. ercv threshold - threshold for ercv interrupt. specified in 64 byte multiples. whenever the number of bytes written in memory for the presently rece ived packet exceeds the ercv threshold, ercv int bit of the interrupt status register is set. rcv counter - this 8 bit value is the ?real time? c ount, in bytes, of the current receive packet (this includes the 4 bytes of status and packet length). the count is rounded to the nearest nibble (16 bytes). the counter is multiplied by 16 decimals to ob tain the number of bytes currently received. notes: ? the value of the rcv counter is in real time asynchrono us format (i.e. the value is constantly changing). it is recommended that the register be read mult iple times to get an accurate reading. ? the rcv counter register will return a value of ?0? when no receive event is occurring.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 58 smsc ds ? LAN91C96I datasheet chapter 8 theory of operation the concept of presentin g the shared ram as a fifo of packets, with a memory management unit allocating memory on a per packet basis responds to the following needs: memory allocation for receive vs. transmit - a fixed partition between receive and transmit area would not be efficient. being able to dynamically allocate it to transmit and receive represents almost the equivalent of duplicating the memory size for some workstation type of drivers. software overhead - by presenting a fifo of packets, the software driver does not have to waste any time in calculating pointers for the different buffers that ma ke up different packets. the driver usually deals with one packet at a time. with this approach, packets are accessible always at the same fixed address, and access is provided to any byte of the packet. headers can be analyzed without reading out the entir e packet. the packet can be moved in or out with a block move operation. multiple upper layer support - the LAN91C96I facilitat es interfacing to multiple upper layer protocols because of the receive packet processing flexibility. a receive lookahead scheme like odi or ndis drivers is supported by copying a small part of the received packet and letting the upper layer provide a pointer for the rest of the data. if the upper layer indicates it does not want the packet, it can be removed upon a single command. if the upper layer wants a specific part of the packet, a block move operation starting at any particular offset can be done. out of order receive processing is also supported: if memory for one packet is not yet available, receive packet processing can continue. efficiency - lacking any level of indirection or linked lis ts of pointers, virtually all the memory is used for data. there are no descriptors, forward links and pointers at all. this simplicity and memory efficiency is accomplished without giving up the benefits of linked lists which is unlimited back-to-back transmission and reception without cpu intervention for as long as memory is available. full duplex support full duplex ethernet operation refers to the ability of the network (or parts of it) to simultaneously transmit and receive packets. the csma/cd protocol used by ethernet for accessing a shared medium is inherently half duplex , and so is the 10base-t phys ical layer where simultaneous transmit and receive activity is interpreted as a collision. the LAN91C96I supports two types of full duplex operation: 1. full duplex mode for diagnostic purposes only, where the received packet is the transmit packet being looped back. this mode is enabled using the fduplx bit in the tcr. in this mode the csma/cd algorithm is used to gain access to the media. 2. fdse (full duplex switched ethernet). enabled by fdse bit in tcr bit. when the LAN91C96I is configured for fdse, its transmit and receive path s will operate independently with carrier sense csma/cd function disabled. note: in fdse mode the packets are not looped back internally. the loopback (full duplex for diagnostics (fduplx)) function of 10base-t transceivers is pe rmanently engaged. it presents the transmit pair waveform to the receive circuit intern ally. this function allows the receiver to see the controller?s own transmission, not only to permit diagnostics, but also to ensure sure that t he node defers to its own transmission - as specified in 802.3.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 59 rev. 03-28-07 datasheet behavior in fdse mode a) no deferral - the transmit channel is dedicated an d always available - the device transmits whenever it has a packet ready to be sent, while respecting the interframe spacing between transmit packets. b) no collision detection - there are no collisions in a switched full duplex environment. magic packet support if the wakeup_en bit in the control register (bank1, offset c) is set, the controller will generate the interrupt; if this bit is not set, this functionality is disabled. setting (1 ) the bit is meaningful only if the function is enabled. for local bus mode, when wakeup_en bi t in control register (bank1, offset c) is set, the controller is set ready for scanning of magic packet, the device will not drop into lower power state. when a magic packet is received, the ethernet contro ller will generate an interrupt causing the host to initiate a service routine to find the source of the event. the interrupt bit in the ecsr is also set if the host plans on polling the controller for wakeup status.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 60 smsc ds ? LAN91C96I datasheet 8.1 typical flow of events for transmit (auto release =0) s/w driver mac side 1 issue allocate memory for tx - n bytes - the mmu attempts to allocate n bytes of ram. 2 wait for successful completion code - poll until the alloc int bit is set or enable its mask bit and wait for the interrupt. the tx packet number is now at the allocation result register. 3 load transmit data - copy the tx packet number into the packet number register. write the pointer register, then use a block move operation from the upper layer transmit queue into the data register. 4 issue "enqueue packet number to tx fifo" - this command writes the number present in the packet number register into the tx fifo. the transmission is now enqueued. no further cpu intervention is needed until a transmit interrupt is generated. 5 the enqueued packet will be transferred to the mac block as a function of txena (ntcr) bit and of the deferral process (1/2 duplex mode only) state. 6 a) upon transmit completion the first word in memory is written with the status word. the packet number is moved from the tx fifo into the tx completion fifo. interrupt is generated by the tx completion fifo being not empty. b) f a tx failure occurs on any packets, tx int is generated and txena is cleared, transmission sequence stops. the packet number of the failure packet is presented at the tx fifo ports register. 7 a) service interrupt - read interrupt status register. if it is a transmit interrupt, read the tx fifo packet number from the fifo ports register. write the packet number into the packet number register. the corresponding status word is now readable from memory. if status word shows successful transmission, issue release packet number command to free up the memory used by this packet. remove packet number from completion fifo by writing tx int acknowledge register. b) option 1) release the packet. option 2) check the transmit status in the eph status register, write the packet number of the current packet to the packet number register, re-enable txena, then go to step 4 to start the tx sequence again.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 61 rev. 03-28-07 datasheet 8.2 typical flow of events for transmit (auto release = 1) s/w driver mac side 1 issue allocate memory for tx - n bytes - the mmu attempts to allocate n bytes of ram. 2 wait for successful completion code - poll until the alloc int bit is set or enable its mask bit and wait for the interrupt. the tx packet number is now at the allocation result register. 3 load transmit data - copy the tx packet number into the packet number register. write the pointer register, then use a block move operation from the upper layer transmit queue into the data register. 4 issue "enqueue packet number to tx fifo" - this command writes the number present in the packet number register into the tx fifo. the transmission is now enqueued. no further cpu intervention is needed until a transmit interrupt is generated. 5 the enqueued packet will be transferred to the mac block as a function of txena (ntcr) bit and of the deferral process (1/2 duplex mode only) state. 6 transmit pages are released by transmit completion. 7 a) the mac generates a txempty interrupt upon a completion of a sequence of enqueued packets. b) if a tx failure occurs on any packets, tx int is generated and txena is cleared, transmission sequence stops. the packet number of the failure packet is presented at the tx fifo ports register. 8 a) service interrupt ? read interrupt status register, exit the interrupt service routine. b) option 1) release the packet. option 2) check the transmit status in the eph status register, write the packet number of the current packet to the packet number register, re-enable txena, then go to step 4 to start the tx sequence again.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 62 smsc ds ? LAN91C96I datasheet 8.3 typical flow of events for receive s/w driver csma/cd side 1 enable reception - by setting the rxen bit. 2 a packet is received with matching address. memory is requested from mmu. a packet number is assigned to it. additional memory is requested if more pages are needed. 3 the internal dma logic generates sequential addresses and writes the receive words into memory. the mmu does the sequential to physical address translation. if overrun, packet is dropped and memory is released. 4 when the end of packet is detected, the status word is placed at the beginning of the receive packet in memory. byte count is placed at the second word. if the crc checks correctly the packet number is written into the rx fifo. the rx fifo being not empty causes rcv int (interrupt) to be set. if crc is incorrect the packet memory is released and no interrupt will occur. 5 service interrupt - read the interrupt status register and determine if rcv int is set. the next receive packet is at receive area. (its packet number can be read from the fifo ports register). the software driver can process the packet by accessing the rx area, and can move it out to system memory if desired. when processing is complete the cpu issues the remove and release from top of rx comm and to have the mmu free up the used memory and packet number.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 63 rev. 03-28-07 datasheet figure 8.1 ? interrupt service routine isr save bank selec & address ptr registerst mask interrupts read interrupt register call tx intr or txempty intr tx intr? get next tx rx intr? yes no no yes call rxintr alloc intr? no yes write allocated pkt# into packet number reg. write ad ptr reg. & copydata & source address enqueue packet packet available for transmission? yes no call allocate eph intr? no yes call eph intr set "ready for packet" flag return buffers to upper layer disable allocation interrupt mask restore address pointer & bank select registers unmask interrupts exit isr
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 64 smsc ds ? LAN91C96I datasheet figure 8.2 ? rx intr rx intr write ad. ptr. reg. & read word 0 from ram destination multicast? read words 2, 3, 4 from ram for address filtering address filtering pass? status word ok? do receive lookahead get copy specs from upper layer okay to copy? copy data per upper layer specs issue "remove and release" command return to isr ye s n o ye s no no yes no yes
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 65 rev. 03-28-07 datasheet tx interrupt with auto_release = false 1. save the packet number register saved_pnr = read byte (bank 2, offset 2) 2. read the eph status register temp = read (bank 0, offset 2) 3. acknowledge tx interrupt write byte (0x02, (bank 2, offset c)); 4. check for status of transmission if ( temp and 0x0001) { //if successful transmission step 4.1.1: issue mmu release (release specific packet) write (0x00a0, (bank2, offset 0)); step 4.1.2: return from the routine } else { //transmission has failed // now we can either release or re-enqueue the packet step 4.2.1: get the packet to release/re-enqueue, stored in fifo temp = read (bank 2, offset 4) temp = temp & 0x003f step 4.2.2: write to the pnr write (temp, (bank2, offset 2)) step 4.2.3 // option 1: release the packet write (0x00a0, (bank2, offset 0)); //option 2: re-enqueue the packet write (0x00c0, (bank2, offset 0)); step 4.2.4: re-enable transmission temp = read(bank0, offset 0); temp = temp2 or 0x0001 write (temp2, (bank 0, offset 0)); step 4.2.5: return from the routine } 5. restore the packet number register write byte (saved_pnr, (bank 2, offset 2)) figure 8.3 ? tx intr
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 66 smsc ds ? LAN91C96I datasheet figure 8.4 ? txempty intr (assumes auto release option selected) txempty intr write acknowledge reg. with txempty bit set read txempty & tx intr acknowledge txintr re-enable txena return to isr issue "release" command restore packet number txempty = 0 & txint = 0 (waiting for completion) txempty = x & txint = 1 (transmission failed) txempty = 1 & txint = 0 (everything went through successfully) read pkt. # register & save write address pointer register read status word from ram update statistics update variables
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 67 rev. 03-28-07 datasheet figure 8.5 ? driver send and allocate routines allocate issue "allocate memory" command to mmu read interrupt status register enqueue packet set "ready for packet" flag return copy remaining tx data packet into ram return buffers to upper layer write allocated packet into packet # register write address pointer register copy part of tx data packet into ram write source address into proper location store data buffer pointer clear "ready for packet" flag enable allocation interrupt allocation passed? ye s n o driver send choose bank select register 2 call allocate exit driver send read allocation result register
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 68 smsc ds ? LAN91C96I datasheet 8.4 memory partitioning unlike other controllers, the lan9 1c96i does not require a fixed memory partitioning between transmit and receive resources. the mmu allocates and de-allocates memory upon different events. an additional mechanism allows the cpu to prevent the receive pr ocess from starving the transmit memory allocation. memory is always requested by the side that needs to write into it, that is: the cpu for transmit or the csma/cd for receive. the cpu can control the number of bytes it req uests for transmit but it cannot determine the number of bytes the receive process is going to demand. furthermore, the receive process requests will be dependent on network traffic, in par ticular on the arrival of broadcast and multicast packets that might not be for the no de, and that are not subject to upp er layer software flow control. in order to prevent unwanted traffic from usin g too much memory, the cpu can program a "memory reserved for transmit" parame ter. if the free memory falls below the "memory reserved for transmit" value, mmu requests from the csma/cd block will fail an d the packets will overrun and be ignored. whenever enough memory is released, packets can be received again. if the reserved value is too large, the node might lose data which is an abnormal condition. if the value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. note that with the memory management built into the LAN91C96I, the cpu can dynamically program this parameter. for instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memo ry). whenever the driver needs to burst transmissions it can reduce the receive memory allocation. the driver program the parameter as a function of the following variables: 1. free memory (read only register) 2. memory size (read only register) the reserved memory value can be changed on the fl y. if the memory reserved for tx value is increased above the free memory, receive packets in progress are still received, but no new packets are accepted until the free memory increases above t he memory reserved value. 8.5 interrupt generation the interrupt strategy for the transmit and receive processes is such that it does not represent the bottleneck in the transmit and receive queue management between the software driver and the controller. for that purpose there is no regi ster reading necessary before the next element in the queue (namely transmit or receive packet) can be handled by the cont roller. the transmit and receive results are placed in memory. the receive interrupt will be generated when the receiv e queue (fifo of packets) is not empty and receive interrupts are enabled. this allows the interrupt serv ice routine to process many receive packets without exiting, or one at a time if the isr just returns after processing and removing one. there are two types of transmit interrupt strategies: 1. one interrupt per packet. 2. one interrupt per sequence of packets. the strategy is determined by how the transmit interrupt bits and the auto release bit are used. tx int bit - set whenever the tx completion fifo is not empty.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 69 rev. 03-28-07 datasheet tx empty int bit - set whenever the tx fifo is empty. auto release - when set, successful transmit packets are not written into completion fifo, and their memory is released automatically. 1. one interrupt per packe t: enable tx int, set auto release=0. the software driver can find the completion result in memory and process the interrupt one packet at a time. depending on the completion code the driver will take different actions . note that the transmit process is working in parallel and other transmissions might be taking place. the LAN91C96I is virtually queuing the packet numbers and their status words. in this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the tx fifo packet number at the fifo ports register. this eliminates the need for the driver to keep a list of packet numbers bei ng transmitted. the numbers are queued by the LAN91C96I and provided back to the cpu as their transmission completes. 2. one interrupt per sequence of packets: enable tx empty int and tx int, set auto release=1. tx empty int is generated only after transmitting the last packet in the fifo. tx int will be set on a fatal transmit error allowing the cpu to know t hat the transmit process has stopped and therefore the fifo will not be emptied. this mode has the advantage of a sm aller cpu overhead, and faster memo ry de-allocation. note that when auto release=1 the cpu is not provid ed with the packet numbers that completed successfully. note : the pointer register is shared by any process accessing the LAN91C96I memory. in order to allow processes to be interruptible, the interrupting proce ss is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt. typically there would be three processes using the pointer: transmit loading (sometimes interrupt driven) receive unloading (interrupt driven) transmit status reading (interrupt driven). 1) and 3) also share the usage of the packet number register. therefore saving and restoring the pnr is also required from interrupt service routines.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 70 smsc ds ? LAN91C96I datasheet 8.6 power down the LAN91C96I can enter power down mode by means of the pwrdwn pin (pin 68) or the pwrdn bit (control register, bit 13). when in power down mode, the LAN91C96I will: ? stop the crystal oscillator ? tristate: data bus interrupts(only by pwrdn bit) niocs16 10base-t and aui outputs turn off analog bias currents ? drive the eeprom and rom outputs inactive ? preserve contents of registers and memory the pwrdwn pin is internally gated with the r eset (reset pin before de-glitching) and with the sreset bit (cor bit 7). this gating function internal ly negates power down whenever reset is high or sreset is high to allow the oscillator to run during r eset. except for this gating function, all other uses of the reset pin use a de-glitched version of the signal as defined in the pin description section. nxendec pin pwrdn pin pwrdn bit 0 1 1 x x 0 1 x 0 0 0 1 normal external endec operation normal internal endec operation powerdown - normal mode restored by pwrdwn pin going low powerdown - bit is cleared by a write access to any LAN91C96I register or by hardware reset
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 71 rev. 03-28-07 datasheet figure 8.6 ? interrupt generation for transmit; receive, mmu t x f i f o t x c o m pl e t i o n f i f o r x f i f o c s m a / c d l o g i c al a d d r e s s p a c k et # m m u ph y s i c a l ad d r e s s r a m cpu address csma address rx packet number rx fifo packet number packet number register pac k # o ut m.s. bit only 'empty' 'not empty' tx done packet number 'not empty' interrupt status register rcv int tx empty int tx int alloc int two options
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 72 smsc ds ? LAN91C96I datasheet chapter 9 functional description of the blocks 9.1 memory management unit the mmu interfaces the on-chip ram on one side an d the arbiter on the other for address and data flow purposes. for allocation and de-allocation, it interfaces the arbiter only. the mmu deals with a single ported memory and is not aware of the fact that there are two entities requesting allocation and actually accessing memory. the mapping function done by the mmu is only a function of the packet number accessed and of the offs et within that packet being accessed. it is not a function of who is requesting the acce ss or the direction of the access. to accomplish that, memory accesses as well as mmu allocation and de-allocation requests are arbitrated by the arbiter block before reaching the mmu. memory allocation could take some time, but the allo c int bit in interrupt status register is negated immediately upon allocation request, allowing the system to poll that register at any time. memory de- allocation command completion indication is provided via the busy bit, readable through the mmu command register. the mapping and queuing functions of the mmu rely on the uniqueness of the packet number assigned to the requester. for that purpose the packet number assignment is c entralized at the mmu, and a number will not be reused until the memory associated with it is released. it is clear that a packet number should not be released while the number is in the tx or rx packet queue. the tx and rcv fifos are deep enough to handle the total number of packets the mmu can allocate, therefore there is no need for the programmer or the hardware to check fifo full conditions. 9.2 arbiter the function of the arbiter is to sequence packet ra m accesses as well as mmu requests in such a way that the on-chip single ported ram and a single mmu can be shared by two parties. one party is the host cpu and the other party is the csma/cd block. the arbiter is address transparent, namely, any address can be accessed at any time. in order to exploit the sequential nature of the access, and minimize t he access time on the system side, the cpu cycle is buffered by the data register rather than go directly to and from memory. whenever a write cycle is performed, the data is written into the data register a nd will be written into memory as a result of that operation, allowing the cpu cycle to complete befor e the arbitration and memory cycle are complete. whenever a read cycle is performed, the data is prov ided immediately from the data register, without having to arbitrate and complete a memory cycle. t he present cycle results in an arbitration request for the next data location. loading the point er causes a similar pre-fetch request. this type of read-ahead and write-behind arbitration allo ws the controller to have a very fast access time, and would work without wait states for as long as the cy cle time specification is satisfied. the values are 40 ns access time, and 185ns cycle time. by the same token, csma/cd cycles might be postponed. the worst case csma/cd latency for arbiter service is one memory cycle. the arbiter uses the pointer register as the cpu provided address, and the internal dma address from the csma/cd side as the addresses to be provided to the mmu.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 73 rev. 03-28-07 datasheet the data path routed by the arbite r goes between memory (the data path does not go through the mmu) on one side and either the cpu side bus or the data path of the csma/cd core. the data path between memory and the data register is in fact buffered by a small fifo in each direction. the fifos beneath the data register can be read and written as bytes or words, in any sequential combination. the presence of these fifos makes sure that word transfers are possible on the system bus even if the address loaded into the pointer is odd. 9.3 bus interface the bus interface handles the data, address and control interfaces and is compliant with the local bus. the functions in this block in clude address decoding for i/o and rom memory (including address relocation support) for local bus, data path routing, sequential memory address support, optional wait state generation, boot ro m support, eeprom setup function, bus transceiver control, and interrupt generation / selection. for local bus, i/o address decoding is done by com paring a15-a4 to the i /o base address determined in part by the upper byte of the base address register, and also requiring that aen be low. if the above address comparison is satisfied and the LAN91C96I is in 16 bit mode, niocs16 will be asserted (low). a valid comparison does not yet indicate a valid i/o cycl e is in progress, as the addresses could be used for a memory cycle, or could even glitch through a valid value. for local bus, only when niord or niowr are activated the i/o cycle begins. 9.4 wait state policy the LAN91C96I can work on most system buses withou t having to add wait states. the two parameters that determine the memory access pr ofile are the read access time and the cycle time into the data register. the read access time is 40ns and the cycle time is 185ns. if any one of them does not satisfy the application requirements, wait states should be added. if the access time is the problem, iochrdy should be negated for all accesses to the LAN91C96I. this can be achieved by programming the no wait st bit in the configuration register to ?0?. the LAN91C96I will negate iochrdy for 100ns to 150ns on every access to any register. if the cycle time is the problem, programming no wait st as described before will solve it but at the expense of slowing down all accesses. the alter native is to let the LAN91C96I negate iochrdy only when the data register fifos require so. namely, if no wait st is set, iochrdy will only be negated if a data register read cycle starts and there is less than a full word in the read fifo, or if a write cycle starts and there is more than two bytes in the write fifo. the cycle time is defined as the time between leading edges of read from the data register, or equivalently between trailing edges of write to the data register. for example, in an local bus system the cycle time of a 16 bit transfer will be at least 2 clocks for the i/o a ccess to the LAN91C96I (+ one clock for the memory cycle) for a total of 3 clocks. in absolute time it means 375n s for an 8mhz bus, and 240ns for a 12.5 mhz bus. the cycle time will not increase when configured for full duplex mode, because the csma/cd memory arbitration requests are sequenced by the dma logic and never overlap.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 74 smsc ds ? LAN91C96I datasheet 9.5 arbitration considerations the arbiter exploits the sequential nature of the cpu ac cesses to provide a very fast access time. memory bandwidth considerations will have an effect on t he cpu cycle time but no effect on access time. for normal 8mhz, 10mhz, and 12.5mhz local bus, as well as eisa normal cycles, the LAN91C96I can be accessed without negating ready. when write operations occur, the data is written into a fifo. the cpu cycle can complete immediately, and the buffered data will be written into memory later. the memory arbitration request is generated as a function of that fifo being not empt y. the nature of the cycle requested (byte/word) is determined by the lsb of the pointer and the number of bytes in the fifo. when read operations occur, words are pre-fetched upon pointer loading in order to have at least a word ready in the fifo to be read. new pre-fetch cycles ar e requested as a function of the number of bytes in the fifo.for example, if an odd pointer value is load ed, first a byte is pre-fetched into the fifo, and immediately a full word is pre-fetched completing three bytes into the fifo. if the cpu reads a word, one byte will be left again a new word is pre-fetched. in the case of write, if an odd point er value is loaded, and a full word is written, the fifo holds two bytes, the first of which is immediately written into an odd me mory location. if by that time another byte or word was written, there will be two or three bytes in the fifo and a full word can be written into the now even memory address. when a csma/cd cycle begins, the arbiter will rout e the csma/cd dma addresses to the mmu as well as the packet number associated with the operation in progress. in full-duplex mode, receive and transmit requests are alternated in such a way that th e cpu arbitration cycle time is not affected. 9.6 dma block the dma block resides between the csma/cd block and the arbiter. it can interface both the data path and the control path of the csma/cd block for different operations. its functions include the following: ? start transmission process into the csma/cd block. ? generate csma/cd side addresses for accessing memory during transmit and receive operations. ? generate mmu memory requests and verify success. ? compute byte count and write it in first locations of receive packet. ? write transmit status word in first locations of transmit packet. ? determine if enough memory is available for reception. ? de-allocate transmit memory after suitable completion. ? de-allocate receive memory upon error conditions. ? initiate retransmissions upon collisions (if less than 16 retries). ? terminate reception and release memory if packet is too long.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 75 rev. 03-28-07 datasheet the specific nature of each opera tion and its trigger event are: 1. tx operations will begin if txena is set and tx fi fo is not empty. the dma logic does not need to use the tx packet number, it goes directly from the fifo to the mmu. however the dma logic controls the removal of the packet number from the fifo. 2. generation of csma/cd side ad dresses into memory: independent 11-bit counters are kept for transmit and receive in order to allow full-duplex operation. 3. mmu requests for allocation are generated by the dma logic upon reception. the initial allocation request is issued when the csma block indicates an ac tive reception. if alloca tion succeeds, the dma block stores the packet number assigned to it, and generates write arbitration requests for as long as the csma/cd fifo is not empty. in parallel the csma/cd completes t he address filtering and notifies the dma of an address match. if there is no address match, the dma logic will release the allocated memory and stop reception. 4. when the csma/cd block notifies the dma logic t hat a receive packet was completed, if the crc is ok, the dma will either write the previously stored packet number into the rx packet number fifo (to be processed by the cpu), or if the crc is bad the dma will just issue a release command to the mmu (and the cpu will never see that packet). packets with bad crc can be received if the rcv_bad bit in the configuration register is set. 5. if auto_release is set, a release is issued by the dma block to the mmu after a successful transmission (tx_succ set), and the tx completion fifo is clocked together with the tx fifo preventing the packet number from moving into the tx completion fifo. 6. based on the rx counter value, if a receive pa cket exceeds 1532 bytes, reception is stopped by the dma and the rx abort bit in the receive control re gister is set. the memory allocated to the packet is automatically released. 7. if an allocation fails, the csma/cd block will activate rx_ovrn int upon detecting a fifo full condition. rxen will stay active to allow rece ption of subsequent packets if memory becomes available. the csma/cd block will flus h the fifo upon the new frame arrival. 9.7 packet number fifos the transmit packet fifo stores the packet numbers awaiting transmission, in the order they were enqueued. the fifo is advanced (written) when the cpu issues the "enqueue packet number command", the packet number to be written is provided by the cpu via the packet number register. the number was previously obtained by requesting memory allocation from the mmu. the fifo is read by the dma block when the csma/cd block is ready to procee d on to the next transmission. by reading the tx empty int bit the cpu can determine if this fifo is empty. the transmit completion fifo stores the packet num bers that were already transmitted but not yet acknowledged by the cpu. the cpu can read the next packet number in this fifo from the fifo ports register. the cpu can remove a packet number from this fifo by issuing a tx int acknowledge. the cpu can determine if this fifo is empty by read ing the tx int bit or the fifo ports register. the receive packet fifo stores the packet numbers already received into memory, in the order they were received. the fifo is advanced (written) by the dma block upon reception of a complete valid packet into memory. the number is determined the moment the dm a block first requests memory from the mmu for that packet. the first receive packet number in the fi fo can be read via the fifo ports register, and the data associated with it can be accessed through the receive area. the packet number can be removed from the fifo with or without an automat ic release of its associated memory.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 76 smsc ds ? LAN91C96I datasheet the fifo is read out upon cpu command (remove packe t from top of rx fifo, or remove and release command) after processing the receive packet in the receive area. the width of each fifo is 5 bits per packet number . the depth of each fifo equals the number of packets the LAN91C96I can handle (18). the guideline is software transparency; the software driver should not be aware of different devices or fifo depths. if the mmu memory allocation succeeded , there will be room in the transmit fifo for enqueuing the packet. conversely if there is free memo ry for receive, there should be room in the receive fifo for storing the packet number. note that the cpu can enqueue a transmit command with a packet number that does not follow the sequence in which the mmu assigned packet numbers. for example, when a transmission failed and it is retried in software, or when a receive packe t is modified and sent back to the network. t x f i f o c o m p l e t i o n f i f o r x f i f o c s m a / c d l o g i c a l a d d r e s s p a c k e t # m m u p h y s i c a l a d d r e s s r a m cpu address csma address rx packet number rx fifo packet number packet number register pack # o ut tx done packet number allocation result registe r allocate release pa c k # o u t dma rd wr tx decoder mmu command register allocate release int figure 9.1 - mmu packet number flow and relevant registers 9.8 csma block the csma/cd block is first interfaced via its cont rol registers in order to define its operational configuration. from then on, t he dma interface between the csma/cd block and memory is used to transfer data to and from its data path interface.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 77 rev. 03-28-07 datasheet for transmit, the csma/cd block will be asked to transmit frames as soon as they are ready in memory. it will continue transmissions until any of the following transmit error occurs: 1. collisions on same frame 2. late collision 3. lost carrier sense and mon_csn set 4. transmit underrun 5. sqet error and stp_sqet set in that case txena will be cleared and the cpu should restart the transmission by setting it again. if a transmission is successful, txena stays set and the csma/cd is provided by the dma block with the next packet to be transmitted. for receive, the cpu sets rxen as a way of star ting the csma/cd block receive process. the csma/cd block will send data after address filtering through the da ta path to the dma block. data is transferred into memory as it is received, and the final check on data acceptance is the crc checking done by the csma/cd block. in any case, the dma takes care of requesting/releasing memory for receive packets, as well as generating the byte count. the receive status word is provided by the csma/cd block and written in the first location of the receive structure by the dma block. if configured for stori ng crc in memory, the csma/cd unit will transfer the crc bytes through the dma interface, and t hen will be treated like regular data bytes. note that the receive status word of any packet is available only through memory and is not readable through any other register. in order to let the cpu know about receive overruns, the rx_ovrn int is set and latched in the interrupt status register, which is readable by the cpu at any time. the address filtering is done inside the csma/cd bl ock. a packet will be received if the destination address is broadcast, or if it is addressed to the indivi dual address of the LAN91C96I, or if it is a multicast address and almul bit is set, or if it is a multicast addr ess matching one of the mult icast table entries. if the prms bit is set, all packets are received. the csma/cd block is a full duplex machine, and wh en working in full duplex mode, the csma/cd block will be simultaneously using its data path transmit and receive interfaces. statistical counters are kept by t he csma/cd block, and are readable through the appropriate register. the counters are four bits each, and can generate an interrupt when reaching their maximum values. software can use that interrupt to update statistics in me mory, or it can keep the counter interrupt disabled, while relying on the transmit interrupt routine reading the counters. given that the counters can increment only once per transmit, this technique is a good comple ment for the single interrupt per sequence strategy. the interface between the csma/cd block and memory is word oriented. two bi-directional fifos make the data path interface. whenever a normal collision occurs (less than 16 retr ies), the csma/cd will trigger the backoff logic and will indicate the dma logic of the collision. the dma is responsible for restarting the data transfer into the csma/cd block regardless of whether the collision happened on the preamble or not. only when 16 retries are reached, the csma/cd block will clear the txena bit, and cpu intervention is required. the dma will not aut omatically restart data transfer in th is case, nor will it transmit the next enqueued packet until txena is set by the cpu. the dma will move the packet number in question from the tx fifo into the tx completion fifo.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 78 smsc ds ? LAN91C96I datasheet 9.9 network interface the LAN91C96I includes both an aui interface for thick and thin coax applications and a 10base-t interface for twisted pair applicati ons. functions common to both are: 1. manchester encoder/decoder to convert nrz data to manchester encoded data and back. 2. a 32ms jabber timer to prevent inadvertently long transmissions. when 'jabbing' occurs, the transmitter is disabled, automatic loopback is disa bled (in 10base-t mode), and a collision indication is given to the controller. the interface 'unjabs' when the transmitter has been idle for a minimum of 256 ms. 3. a phase-lock loop to recover data and clock from the manchester data stream with up to plus or minus 18ns of jitter. 4. diagnostic loopback capability. 5. led drivers for collision, tr ansmission, reception, and jabber. 9.10 10base-t the 10base-t interface conforms to the twisted pair mau addendum to t he 802.3 specific ation. on the transmission side, it converts t he nrz data from the controller to manchester data and provides the appropriate signal level for driving the media. signal are predistorted before transmission to minimize isi. the collision detection circuitry monitors the simulta neous occurrence of received signals and transmitted data on the media. during transmissi on, data is automatically looped ba ck to the receiver except during collision periods, in which case the input to the receiver is network data. during collisions, should the receive input go idle prior to the transmitter going idle, input to the receiver switc hes back to t he transmitter within nine bit times. following transmission, the transmitter performs a sqe test. this test exercises the collision detection circuitry within the 10base-t interface. the receiver monitors the media at all times. it re covers the clock and data and passes it along to the controller. in the absence of any receive activity, the transmitter is looped back to the receiver. in addition, the receiver performs aut omatic polarity correction. the 10base-t interface performs link integrity tests per section 14.2.1.7 of 802.3, using the following values: 1. link_loss_timer: 64 ms 2. link_test_min_timer: 4 ms 3. link_count: 2 4. link_test_max_timer: 64 ms the state of the link is reflected in the ephsr. 9.11 aui the LAN91C96I also provides a standard six wire aui interface to a coax transceiver.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 79 rev. 03-28-07 datasheet 9.12 physical interface the internal physical interface (phy) consists of an encoder/decoder (endec) and an internal 10base-t transceiver. the endec also provides a standard 6-pin aui interface to an external coax transceiver for 10base-2 and 10base-5 applications. the internal signals between mac and the phy can be routed to pins by asserting the nxendec pin low. this feature allows the interface to an external endec and transceiver. the phy functions can be divided into transmit and receive functions. 9.13 transmit functions manchester encoding the phy encodes the transmit data received from the mac. the encoded data is directed internally to the selected output driver for transmission over the twis ted-pair network or the aui cable. data transmission and encoding is initiated by the transmit enable input, txe, going low. 9.14 transmit drivers the encoded transmit data passes through to the transmi t driver pair, tpetxp(n), and its complement, tpetxdp(n). each output of the transmit driver pai r has a source resistance of 10 ohms maximum and a current rating of 25 ma maximum. the degree of pred istortion is determined by the termination resistors; the equivalent resistance should be 100 ohms. jabber function this integrated function prevents the dte from locking into a c ontinuous transmit state. in 10base-t mode, if transmission continues beyon d the specified time limit, the ja bber function inhibits further transmission and asserts the collision indicator ncoll. the limits for jabber transmission are 20 to 15 ms in 10base-t mode. in the aui mode, the jabber f unction is performed by the external transceiver. sqe function in the 10base-t mode, the phy supports the signal quality error (sqe) function. at the end of a transmission, the phy asserts the ncoll signal for 10+/- 5 bit times beginning 0.6 to 1.6ms after the last positive transition of a trans mitted frame. in the aui mode, the sqe function is performed by the external transceiver. 9.15 receive functions receive drivers differential signals received off the twisted-pair network or aui cable are directed to the internal clock recovery circuit prior to being decoded for the mac. manchester decoder and clock recovery the phy performs timing recovery and manchester decoding of incoming differential signals in 10base-t or aui modes, with its built-in phase-lock loop (pll ). the decoded (nrz) data, rxd, and the recovered clock, rxclk, becomes available to t he mac, typically within 9 bit times (5 for aui) after the assertion of ncrs. the receive clock, rxclk, is phase-locked to the transmit clock in the absence of a received signal (idle).
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 80 smsc ds ? LAN91C96I datasheet squelch function the integrated smart squelch circuit employs a comb ination of amplitude and timing measurements to determine the validity of data received off the network . it prevents noise at the differential inputs from falsely triggering the decoder in the absence of valid data or link test pulses. signal levels below 300mv (180mv for aui) or pulse widths less than 15ns at the differential inputs are rejected. signals above 585mv (300mv for aui) and pulse widths greater than 30ns will be accepted. when using the extended cable mode with 10base-t media which extends beyon d the standard limit of 100 meters, the squelch level can optionally be set to reject signals below 180mv and accept signals above 300mv. if the input signal exceeds the squelch requirements, t he carrier sense output, ncrs, is asserted. reverse polarity function in the 10base-t mode, the phy monitors for receiver polarity reversal due to crossed wires and corrects by reversing the signal internally. collision detection function in the 10base-t mode, a collision state is indica ted when there are simultaneous transmissions and receptions on the twisted pair link. during a collisi on state, the ncoll signal is asserted. if the received data ends and the transmit control signal is still active , the transmit data is sent to the mac within 9 bit times. the ncoll signal is de-asserted within 9 bi t times after the collision terminates. in the aui mode, the external transceiver sends a 10mhz signa l to the phy upon detection of a collision. link integrity the phy test for a faulty twisted-pair link. in the absence of transmit data, link test pulses are transmitted every 16+/-8ms after the end of the last transmission or link pulse on the twisted pair medium. if neither valid data nor link test pulses are received within 10 to 150ms, the link is declared bad and both data transmission as well as the operational loopback functi on are disabled. the link integrity function can be disabled for pre-10base-t twisted-pair networks.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 81 rev. 03-28-07 datasheet chapter 10 board setup information the following parameters are obtained from the eeprom as board setup information: ? ethernet individual address ? i/o base address ? rom base address ? 8/16 bit adapter ? 10base-t or aui interface ? interrupt line selection register eeprom word address configuration register base register ios value * 4 (ios value *4) + 1 all the above mentioned values are read from the eeprom upon hardware reset. except for the individual address, the valu e of the ios switches determines the offset within the eeprom for these parameters, in such a way that many identical boar ds can be plugged into the same system by just changing the ios jumpers. in order to support a software utility based insta llation, even if the eeprom was never programmed, the eeprom can be written using the lan9 1c96i. one of the ios combinat ion is associated with a fixed default value for the key parameters (i/o base, rom base, interrupt) that can always be used regardless of the eeprom based value being programmed. this value will be used if all ios pins are left open or pulled high. the eeprom is arranged as a 64 x 16 array. the s pecific target device is the 9346 1024-bit serial eeprom. all eeprom accesses are done in words. all eeprom addresses sh own are specified as word addresses. individual address 20-22 hexif ios2-0 = 7, on ly the individual address is read from the eeprom. currently assigned values are assumed for the other registers. these values are default if the eeprom read operation follows hardware reset. the eeprom select bit is used to determine the type of eeprom operation: a) normal or b) general purpose register. a) normal eeprom operation - eeprom select bit = 0 on eeprom read operations (after reset or a fter setting reload high) the configuration register and base register are updated with the eeprom values at locations defined by the ios2-0 pins. the individual address register s are updated with the values stored in the individual address area of the eeprom. on eeprom write operations (after setting the st ore bit) the values of the configuration register and base register are written in the eeprom locations defined by the ios2-0 pins. the three least significant bits of the co ntrol register (eeprom select, reload and store) are used to control the eeprom. their va lues are not stored nor loaded from the eeprom. b) general purpose register - eeprom select bit = 1
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 82 smsc ds ? LAN91C96I datasheet on eeprom read operations (after setting reload high) the eeprom word address defined by the pointer register 6 least significant bits is read into the general purpose register. on eeprom write operations (after setting the st ore bit) the value of the general purpose register is written at the eeprom word addr ess defined by the pointer register 6 least significant bits. reload and store are set by the user to initiate read and write operations respectively. polling the value until read low is used to determine comple tion. when an eeprom a ccess is in progress the store and reload bits of ctr will read-back as both bits high. no other bits of the LAN91C96I can be read or written until the eeprom operation completes and both bits are clear. this mechanism is also valid fo r reset initiated reloads. note : if no eeprom is connected to t he LAN91C96I, the eneep pin should be grounded an d no accesses to the eeprom will be attempted. confi guration, base a nd individual addresses assu me their default values upon hardware reset and the cpu is responsible for programming them for their final value. 10.1 diagnostic leds the following led drive signals are available for diagnostic and installation aid purposes: ? ntxled - activated by transmit activity. ? nbseled - board select led. activated when t he board space is accessed, namely on accesses to the LAN91C96I register space or the rom area dec oded by the LAN91C96I. the signal is stretched to 125 msec. ? nrxled - activated by receive activity. ? nlinkled - reflects t he link integrity status. 10.2 bus clock considerations the arbiter exploits the sequential nature of the cpu accesses to provide a very fast access time. memory bandwidth considerations will have an effect on the cpu cycle time but no effect on access time. for normal 8mhz, 10mhz, and 12.5mhz local bus, as well as eisa normal cycles, the LAN91C96I can be accessed without negating ready. see arbitration considerations in functional description of the blocks for more details.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 83 rev. 03-28-07 datasheet figure 10.1 - 64 x 16 serial eeprom map configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. configuration reg. base reg. ia0-1 ia2-3 ia4-5 ios2-0 word address 000 0h 1h 4h 5h 8h 9h ch dh 10h 11h 14h 15h 18h 19h 20h 21h 22h 001 010 011 100 101 110 xxx 16 bits
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 84 smsc ds ? LAN91C96I datasheet chapter 11 operation description 11.1 maximum guaranteed ratings* operating temperature range ................................................................................................ -40 q c to 85 q c storage temperatur e range ...............................................................................................-55 q c to +150 q c lead temperature range (sol dering, 10 se conds) ............................................................................+325 q c positive voltage on 3.3v-o nly tolerant i/o pin, wi th respect to gr ound ........................................v cc + 0.3v positive voltage on 5v tolerant i pin, with respect to ground ????????????????? ... 5.5v negative voltage on any pin, with respec t to ground ........................................................................... -0.3v maximum v cc .............................................................................................................................. ......... +5.5v * stresses above those listed above could cause permanent damage to the device. this is a stress rating only and functional operati on of the device at any other condition above those indicated in the operation sections of this specif ication is not implied. note: when powering this device from laboratory or system power supplies, it is im portant that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possib ility exists, it is suggest ed that a clamp circuit be used.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 85 rev. 03-28-07 datasheet 11.2 dc electrical characteristics (t a = -40 q c to 85 q c, v cc = +5.0v 10%, or v cc = +3.3 v 10%) parameter symbol min typ max units comments input voltage levels for v cc = 5.0v i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v ttl levels is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 250 0.8 v v mv schmitt trigger schmitt trigger i clk input buffer low input level high input level v ilck v ihck 3.3 0.4 v v input voltage levels for v cc = 3.3v i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.0 165 0.8 v v mv schmitt trigger schmitt trigger i clk input buffer low input level high input level v ilck v ihck 2.0 0.3 v v input leakage for v cc = 5.0v input leakage (all i and is buffers except pins with pullups/pulldowns) low input leakage high input leakage i il i ih -10 -10 +10 +10 p a p a v in = 0 v in = v cc
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 86 smsc ds ? LAN91C96I datasheet (t a = -40 q c to 85 q c, v cc = +5.0v 10%, or v cc = +3.3 v 10%) parameter symbol min typ max units comments input leakage for v cc = 3.3v input leakage (all i and is buffers except pins with pullups/pulldowns) low input leakage high input leakage i il i ih -10 -10 +10 +10 p a p a v in = 0 v in = v cc input current for v cc = 5.0v ip type buffers input current i il -150 -50 p a v in = 0 id type buffers input current i ih +50 +150 p a v in = v cc input current for v cc = 3.3v ip type buffers input current i il -100 -50 p a v in = 0 id type buffers input current i ih +50 +100 p a v in = v cc output voltage for v cc = 5.0v i/o4 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.4 +10 v v p a i ol = 4 ma i oh = -2 ma v in = 0 to v cc i/o24 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.5 +10 v v p a i ol = 24 ma i oh = -12 ma v in = 0 to v cc o24 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.5 +10 v v p a i ol = 24 ma i oh = -12 ma v in = 0 to v cc
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 87 rev. 03-28-07 datasheet (t a = -40 q c to 85 q c, v cc = +5.0v 10%, or v cc = +3.3 v 10%) parameter symbol min typ max units comments o4 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.4 +10 v v p a i ol = 4 ma i oh = -2 ma v in = 0 to v cc od16 type buffer low output level output leakage v ol i leak -10 0.5 +10 v p a i ol = 16 ma v in = 0 to v cc o162 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.5 +10 v v p a i ol = 16 ma i oh = -2 ma v in = 0 to v cc od24 type buffer low output level output leakage v ol i leak -10 0.5 +10 v p a i ol = 24 ma v in = 0 to v cc output voltage for v cc = 3.3v i/o4 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.4 +10 v v p a i ol = 2 ma i oh = -1 ma v in = 0 to v cc i/o24 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.5 +10 v v p a i ol = 16 ma i oh = -6 ma v in = 0 to v cc o24 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.5 +10 v v p a i ol = 12 ma i oh = -6 ma v in = 0 to v cc
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 88 smsc ds ? LAN91C96I datasheet (t a = -40 q c to 85 q c, v cc = +5.0v 10%, or v cc = +3.3 v 10%) parameter symbol min typ max units comments o4 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.4 +10 v v p a i ol = 2 ma i oh = -1 ma v in = 0 to v cc od16 type buffer low output level output leakage v ol i leak -10 0.5 +10 v p a i ol = 8 ma v in = 0 to v cc o162 type buffer low output level high output level output leakage v ol v oh i leak 2.4 -10 0.5 +10 v v p a i ol = 8 ma i oh = -1 ma v in = 0 to v cc od24 type buffer low output level output leakage v ol i leak -10 0.5 +10 v p a i ol = 12 ma v in = 0 to v cc supply current for v cc = 5.0v supply current active supply current in power down mode i cc i cdwn 50 8 95 ma ma supply current for v cc = 3.3v supply current active supply current in power down mode i cc i cdwn 20 3 64 ma ma xtal2 output drive for v cc = 5.0v xtal2 output drive high i cx2h tbd ma xtal2 output drive low i cx2l tbd ma xtal2 output drive for v cc = 3.3v xtal2 output drive high i cx2h -6 ma @2.4v xtal2 output drive low i cx2l 3 ma @0.4v
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 89 rev. 03-28-07 datasheet capacitance t a = 25 q c; fc = 1mhz; v cc = 5v, or v cc = +3.3v limits parameter symbol min typ max unit test condition clock input capacitance (xtal1) c cin 5 6 pf clock output capacitance (xtal2) c cout 5 6 pf input capacitance c in 10 pf output capacitance c out 20 pf all pins except pin under test tied to ac ground v cc = 5v +/- 10% parameter min typ max units 10base-t receiver threshold voltage 100 mv receiver squelch 300 400 585 mv receiver common mode range 0 v dd transmitter output: voltage source resistance 2 2.5 3 10 v ohms transmitter output dc offset 50 mv transmitter backswing voltage to idle 100 mv differential input voltage 0.585 3 v aui receiver threshold voltage 60 mv receiver squelch 180 240 300 mv receiver common mode range 0 v dd transmitter output voltage (r=78 : ) 0.45 0.85 1.2 v transmitter backswing voltage to idle 100 mv input differential voltage 0.3 1.2 v output short circuit (to v cc or gnd) current 150 ma differential idle voltage (measured 8.0 p s after last positive transit ion of data frame) 40 mv v cc = 3.3v +/- 10% parameter min typ max units 10base-t receiver threshold voltage tbd mv receiver squelch 225 260 520 mv receiver common mode range 0 vdd transmitter output: voltage source resistance +/- 1.3 +/- 1.5 +/- 1.6 10 v ohms transmitter output dc offset 50 mv transmitter backswing voltage to idle 100 mv differential input voltage +/- 0.520 +/- 3 v aui receiver threshold voltage tbd mv receiver squelch 120 140 160 mv
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 90 smsc ds ? LAN91C96I datasheet parameter min typ max units receiver common mode range 0 vdd transmitter output voltage (r=78 : ) +/- 0.39 +/- 0.47 +/- 0.55 v transmitter backswing voltage to idle 100 mv input differential volta ge +/- 0.25 +/- 0.990 v output short circuit (to v cc or gnd) current tbd ma differential idle voltage (measured 8.0 p s after last positive transit ion of data frame) 40 mv capacitive load on outputs niocs16, iochrdy 240 pf intr0-3 120 pf all other outputs 45 pf
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 91 rev. 03-28-07 datasheet chapter 12 timing diagrams figure 12.1 ? local bus consecutive read cycles bale tied high valid address valid address valid data out valid data out t15 t4 t3 t20 t5 t6 z z a0-15 aen, nsbhe niocs16 niord d0-15 t3 t4 t5 t6 t15 t20 address, nsbhe, aen setup to control active address, nsbhe, aen hold after control inactive niord low to valid data niord high to data floating a4-a15, aen low, bale high to niocs16 low cycle time* parameter min typ max units 10 20 185 25 15 12 ns ns ns ns ns ns iochrdy not used - t20 has to be met *note: the cycle time is defined only for consecutive accesses to the data register. these values assume that iochrdy is not used.
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 92 smsc ds ? LAN91C96I datasheet figure 12.2 ? local bus consecutive write cycles valid address valid address t15 t4 t3 t20 a0-15 aen, nsbhe niocs16 niowr d0-15 valid data in valid data t7 t8 bale tied high t3 t4 t7 t8 t15 t20 12 ns ns ns ns ns ns address, nsbhe, aen setup to control active address, nsbhe, aen hold after control inactive data setup to niowr rising data hold after niowr rising a4-a15, aen low, bale high to niocs16 low cycle time* parameter min typ max units 10 5 5 5 185 iochrdy not used - t20 has to be met *note: the cycle time is defined only for consecutive accesses to the data register. these values assume that iochrdy is not used.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 93 rev. 03-28-07 datasheet figure 12.3 ? local bus consecutive read and write cycles t20 a0-15 aen, nsbhe niocs16 niowr d0-d15 valid address valid address niord t9 t10 zz z valid data valid data iochrdy z z control active to iochrdy low iochrdy low pulse width* cycle time** parameter min typ max units 100 185 12 150 ns ns ns t9 t10 t20 *note: assuming no wait st = 0 in configuration register and cycle time observed. **note: the cycle time is defined only for accesses to the data register as follows: for data register read - from niord falling to next niord falling for data register write - from niowr rising to next niowr rising
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 94 smsc ds ? LAN91C96I datasheet figure 12.4 ? data register special read access a0-15 (isa) aen, nsbhe niocs16 d0-d15 niord valid data valid address iochrdy out t9 t18 t19 z z parameter min typ max units 15 575 225 ns ns ns t9 t18 t19 control active to iochrdy low iochrdy width when data is unavailable at data register valid data to iochrdy inactive iochrdy is used instead of meeting t20 and t43. "no wait st' bit is 1 - iochrdy only negated if needed and only for data register access.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 95 rev. 03-28-07 datasheet figure 12.5 ? data register special write access a0-15 (isa) aen, nsbhe niocs16 d0-d15 niowr valid data in valid address iochrdy t18 zz parameter min typ max units 15 425 t9 t18 control active to iochrdy low iochrdy width when data register is full iochrdy is used inst ead of meeting t20 and t44. 'no wait st' bit is 1 - iochrdy only negated if needed and only for data register access. ns ns t9
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 96 smsc ds ? LAN91C96I datasheet figure 12.6 - 8-bit mode register cycles a0-15 (isa) aen niord d0-7 niowr t3 t3 t5 z valid data out z valid data in t7 t8 valid address t3 t5 t7 t8 address, nsbhe, aen setup to control active niord low to valid data data setup to niowr rising data hold after niowr rising parameter min typ max units 25 30 9 40 ns ns ns ns valid address
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 97 rev. 03-28-07 datasheet figure 12.7 ? external rom read access a0-19 nmemrd address valid d0-15 t3 t4 z bale tied high t3 t4 t16 t17 address setup to control active address hold after control inactive nmemrd low to nrom low(internal) nmemrd high to nrom high(internal) parameter min typ max units 10 20 0 0 20 35 ns ns ns ns t16 t17 nrom
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 98 smsc ds ? LAN91C96I datasheet figure 12.8 ? local bus register access when using bale aen niocs16 a0-15, nsbhe niord bale niowr t4 valid t1 t2 t15 t3 t1 t2 t3 t4 t15 address, nsbhe setup to bale falling address, nsbhe hold after bale falling address, nsbhe, aen setup to control active aen hold after control inactive a4-a15, aen low, bale high to niocs16 low parameter min typ max units 12 ns ns ns ns ns t4 not needed. niocs16 not relevant in 8-bit mode. 10 5 25 20 t5 t5 bale pulse width 15 ns
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 99 rev. 03-28-07 datasheet figure 12.9 ? external rom read access using bale address setup to bale falling address hold after bale falling address setup to control active nmemrd low to nrom low nmemrd high to nrom high nmemrd a0-19 nrom bale valid t1 t2 t3 t16 t17 t1 t2 t3 t16 t17 10 5 25 20 35 ns ns ns ns ns parameter mi n ty p unit s max
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 100 smsc ds ? LAN91C96I datasheet figure 12.10 - eeprom read eedi eesk eedo eecs eesk falling to eecs changing t21 parameter min typ max units 15 ns t21 0 9346 is typically the serial eeprom used. t68 t68 eesk falling to eedo changing 25 ns
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 101 rev. 03-28-07 datasheet figure 12.11 - eeprom write eesk eedo eedi eecs eesk falling to eecs changing t69 parameter min typ max units 5ns t69 9346 is typically the serial eeprom used. eesk falling to eedo changing t70 20 ns t70
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 102 smsc ds ? LAN91C96I datasheet figure 12.12 ? external endec interface ? start of transmit figure 12.13 ? external endec interface ? receive data (rxd sampled by falling rxclk) rxd rxclk ncrs t23 t24 t23 ncrs, rxd setup to rxclk falling ncrs, rxd hold after rxclk falling t23 t24 parameter min typ max units ns ns 10 30 ntxen txd txclk t22 t22 t22 min typ max unit u 25 ns 0 parameter txd, ntxen delay from txclk falling
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 103 rev. 03-28-07 datasheet figure 12.14 ? differential output signal timing (10base-t and aui) t petxp t petxn t petxdn t petxdp t xp t xn t31 t32 t33 t34 tpetxp to tpetxn skew tpetxp(n) to tpetxdp(n) delay tpetxdn to tpetxdp skew txp to txn skew parameter min typ max units -1 47 -1 -1.5 +1 53 +1 1.5 ns ns ns ns t31 t31 t32 t32 t33 t33 t34 t34 twisted pair drivers aui drivers
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 104 smsc ds ? LAN91C96I datasheet figure 12.15 ? receive timing ? start of frame (aui and 10base-t) 1101 101010 0 first bit decoded t35 t36 1101 1 01010 0 t37 first bit decoded t38 recp recn ncrs (internal) t perxp(n) ncrs (internal) t35 t36 t37 t38 noise pulse width reject (aui) carrier sense turn on delay (aui) noise sense pulse width reject (10base-t) carrier sense turn on delay (10base-t) parameter min typ max units 15 50 15 450 30 100 30 550 ns ns ns ns 25 70 25 500
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 105 rev. 03-28-07 datasheet ba1/0 last bit tperxp tperxn recp recn ncrs (internal) t39 t39 receiver turn off delay parameter min typ max units 200 300 ns figure 12.16 ? receive timing ? end of frame (aui and 10base-t) ba1/0 last bit tpetxp tpetxn txp txn t40 t41 transmit output high to idle in half-step mode transmit output high before idle in half-step mode parameter min typ max units 200 800 ns ns t40 t41 figure 12.17 ? transmit timing ? end of frame (aui and 10base-t)
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 106 smsc ds ? LAN91C96I datasheet figure 12.18 ? collision timing (aui) figure 12.19 ? memory read timing collp colln t42 t43 col (internal) t42 t43 collision turn on delay collision turn off delay parameter min typ max units 50 350 ns ns address pointer register data register niowr niord iochrdy/ nwait (z) t44 t44 pointer register reloaded to a word of data prefetched into data register parameter min typ max units ns 2 * t20 note: if t44 is not met, iochrdy will be negated for the required time. this parameter can be ignored if iochrdy is connected to the system.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 107 rev. 03-28-07 datasheet figure 12.20 ? input clock timing name description min typ max units t1 clock cycle time for 20 mhz 50 ns t2 clock high time/low time for 20 mhz 30/20 20/30 ns tr, tf clock rise time/fall time 5 ns xtal1 startup time (from 1.6v of vcc rising) 50 msec xtal1 capture range (xtal1 frequency variation) 19.7 20.3 mhz xtal internal feedback resistor 1 3 meg ohm figure 12.21 ? memory write timing address data register pointer register niowr t45 t45 last access to data register to pointer reloaded parameter min typ max units ns 2 * t20 clock t2 t2 t1 tr tf
non-pci single-chip full duplex ethernet controller rev. 03-28-07 page 108 smsc ds ? LAN91C96I datasheet chapter 13 package outlines figure 13.1 - 100 pin qfp package outline table 13.1 - 100 pin qfp package parameters min nominal max remarks a ~ ~ 3.4 overall package height a1 0.05 ~ 0.5 standoff a2 2.55 ~ 3.05 body thickness d 23.65 ~ 24.15 x span d1 19.90 ~ 20.10 x body size e 17.65 ~ 18.15 y span e1 13.90 ~ 14.10 y body size h 0.11 ~ 0.23 lead frame thickness l 0.73 0.88 1.03 lead foot length l1 ~ 1.95 ~ lead length e 0.65 basic lead pitch t 0 o ~ 7 o lead foot angle w 0.20 ~ 0.40 lead width r1 0.10 ~ 0.25 lead shoulder radius r2 0.15 ~ 0.40 lead foot radius ccc ~ ~ 0.10 coplanarity notes: 1 controlling unit: millimeter. 2 tolerance on the true position of the leads is 0.065 mm maximum 3 package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm. 4 dimension for foot length l measured at the gauge plane 0.25 mm above the seating plane. 5 details of pin 1 identifier are optional but must be located within the zone indicated.
non-pci single-chip full duplex ethernet controller smsc ds ? LAN91C96I page 109 rev. 03-28-07 datasheet figure 13.2 - 100 pin tqfp package outline table 13.2 - 100 pin tqfp package parameters min nominal max remarks a ~ ~ 1.20 overall package height a1 0.05 ~ 0.15 standoff a2 0.95 ~ 1.05 body thickness d 15.80 ~ 16.20 x span d1 13.90 ~ 14.10 x body size e 15.80 ~ 16.20 y span e1 13.90 ~ 14.10 y body size h 0.09 ~ 0.20 lead frame thickness l 0.45 0.60 0.75 lead foot length l1 ~ 1.00 ~ lead length e 0.50 basic lead pitch t 0 o ~ 7 o lead foot angle w 0.17 0.22 0.27 lead width r1 0.08 ~ ~ lead shoulder radius r2 0.08 ~ 0.20 lead foot radius ccc ~ ~ 0.08 coplanarity notes: 1 controlling unit: millimeter. 2 tolerance on the true position of the leads is 0.04 mm maximum. 3 package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm. 4 dimension for foot length l measured at the gauge plane 0.25 mm above the seating plane. 5 details of pin 1 identifier are optional but must be located within the zone indicated.

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